Motorola 24-Bit Digital Signal Processor, DSP56000 Start Hardware Loop Operation Assembler Syntax

INSTRUCTION DESCRIPTIONS

	DO	Start Hardware Loop		DO
Operation:		Assembler Syntax:
SP+1 ➞ SP;LA ➞ SSH;LC ➞ SSL;X:ea ➞ LC			DO	X:ea,expr
SP+1 ➞ SP;PC ➞ SSH;SR ➞ SSL;expr –1 ➞ LA
1 ➞ LF
SP+1 ➞ SP;LA ➞ SSH;LC ➞ SSL;X:aa ➞ LC			DO	X:aa,expr
SP+1 ➞ SP;PC ➞ SSH;SR ➞ SSL;expr –1 ➞ LA
1 ➞ LF
SP+1 ➞ SP;LA ➞ SSH;LC ➞ SSL;Y:ea ➞ LC			DO	Y:ea,expr
SP+1 ➞ SP;PC ➞ SSH;SR ➞ SSL;expr –1 ➞ LA
1 ➞ LF
SP+1 ➞ SP;LA ➞ SSH;LC ➞ SSL;Y:aa ➞ LC			DO	Y:aa,expr
SP+1 ➞ SP;PC ➞ SSH;SR ➞ SSL;expr –1 ➞ LA
1 ➞ LF
SP+1 ➞ SP;LA ➞ SSH;LC ➞ SSL;#xxx ➞ LC			DO	#xxx,expr
SP+1 ➞ SP;PC ➞ SSH;SR ➞ SSL;expr –1 ➞ LA
1 ➞ LF
SP+1 ➞ SP;LA ➞ SSH;LC ➞ SSL;S ➞ LC			DO	S,expr
SP+1 ➞ SP;PC ➞ SSH;SR ➞ SSL;expr –1 ➞ LA
1 ➞ LF

End of Loop:

SSL(LF) ➞ SR;SP–1 ➞ SP

SSH ➞ LA;SSL ➞ LC;SP – 1 ➞ SP

Description: Begin a hardware DO loop that is to be repeated the number of times spec- ified in the instruction’s source operand and whose range of execution is terminated by the destination operand (previously shown as “expr”). No overhead other than the execu- tion of this DO instruction is required to set up this loop. DO loops can be nested and the loop count can be passed as a parameter.

During the first instruction cycle, the current contents of the loop address (LA) and the loop counter (LC) registers are pushed onto the system stack. The DO instruction’s source operand is then loaded into the loop counter (LC) register. The LC register con- tains the remaining number of times the DO loop will be executed and can be accessed from inside the DO loop subject to certain restrictions. If LC equals zero, the DO loop is

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