Motorola 24-Bit Digital Signal Processor, DSP56000 manual Jcc, Jump Conditionally

INSTRUCTION DESCRIPTIONS

Jcc	Jump Conditionally
Operation:	Assembler Syntax:
If cc, then 0xxx ➞PC	Jcc xxx
else PC+1 ➞PC
If cc, then ea ➞PC	Jcc xxx
else PC+1 ➞PC

Jcc

Description: Jump to the location in program memory given by the instruction’s effective address if the specified condition is true. If the specified condition is false, the program

counter (PC) is incremented and the effective address is ignored. However, the address register specified in the effective address field is always updated independently of the

specified condition. All memory alterable addressing modes may be used for the effec- tive address. A Fast Short Jump addressing mode may also be used. The 12-bit data is zero extended to form the effective address. See Section A.9 for restrictions. The term “cc” may specify the following conditions:

	“cc” Mnemonic	Condition
CC (HS)	— carry clear (higher or same)	C=0
CS (LO)	— carry set (lower)	C=1
EC	— extension clear	E=0
EQ	— equal	Z=1
ES	— extension set	E=1
GE	— greater than or equal	N ⊕ V=0
GT	— greater than	Z+(N	⊕ V)=0
LC	— limit clear	L=0	⊕ V)=1
LE	— less than or equal	Z+(N
LS	— limit set	L=1
LT	— less than	N ⊕ V=1
MI	— minus	N=1
NE	— not equal	Z=0	•
NR	— normalized	Z+(U		E)=1
PL	— plus	N=0	•
NN	— not normalized	Z+(U
				E)=0

where

U denotes the logical complement of U, + denotes the logical OR operator,

• denotes the logical AND operator, and

⊕ denotes the logical Exclusive OR operator

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