Motorola DSP56000 manual Interrupt Priority Level Bits External Interrupt, Interrupt Sources

EXCEPTION PROCESSING STATE (INTERRUPT PROCESSING)

Table 7-3 Interrupt Priority Level Bits Table 7-4 External Interrupt

xxL1

xxL0

Enabled

IPL

0

0

No

—

with the same IPL are pending, a second fixed-priority structure within that IPL deter- mines which interrupt the processor will service. The fixed priority of interrupts within an IPL and the interrupt enable bits for all interrupts are shown in Table 7-5.

7.3.3 Interrupt Sources

Interrupts can originate from any of the vector addresses listed in Table 7-6,which shows the corresponding interrupt starting address for each interrupt source. These addresses are located in the first 64 locations of program memory.

Table 7-5 Central Processor Interrupt Priorities Within an IPL

Priority

Exception

Enabled By

Bit No.

XData Memory Address

Level 3 (Nonmaskable)

Highest	Hardware RESET		—	—	—
	III		—	—	—
	NMI		—	—	—
	Stack Error		—	—	—
	Trace		—	—	—
Lowest	SWI		—	—	—
		Levels 0, 1, 2 (Maskable)

Higher

IRQA (External Interrupt)

IRQA Mode Bits 0 and 1

$FFFF

Lower

IRQB (External Interrupt)

IRQB Mode Bits 3 and 4

$FFFF

MOTOROLA PROCESSING STATES 7 - 15