Motorola 24-Bit Digital Signal Processor, DSP56000 - page 211

PROGRAM ADDRESS BUS HISTORY BUFFER
MOTOROLA ON-CHIP EMULATION (OnCE) 10 - 19
addresses of the last five instructions that were executed.
10.8.1 PAB Register for Fetch (OPABFR)
The OPABFR is a 16-bit register that stores the address of the last instruction that was
fetched before the debug mode was entered. The OPABFR can only be read through the
OnCE serial interface. This register is not affected by the operations performed during the
debug mode.
10.8.2 PAB Register for Decode (OPABDR)
The OPABDR is a 16-bit register that stores the address of the instruction currently in the
instruction latch. This is the instruction that would have been decoded if the chip would
not have entered the debug mode. OPABDR can only be read through the serial interface.
FETCH ADDRESS (OPABFR)
PAB
PAB FIFO REGISTER 0
DECODE ADDRESS (OPABDR)
CIRCULAR
BUFFER
POINTER
PAB FIFO SHIFT REGISTER DSO
DSCK
PAB FIFO REGISTER 1
PAB FIFO REGISTER 2
PAB FIFO REGISTER 3
PAB FIFO REGISTER 4
Figure 10-9 OnCE PAB FIFO