Motorola 24-Bit Digital Signal Processor Jump to Subroutine Conditionally, Cc Mnemonic Condition

INSTRUCTION DESCRIPTIONS

	JScc	Jump to Subroutine Conditionally		JScc
Operation:			Assembler Syntax:
If cc, then SP+1➞SP; PC➞SSH; SR➞SSL; 0xxx➞PC			JScc xxx
	else PC+1➞PC
If cc, then SP+1➞SP; PC➞SSH; SR➞SSL; ea➞PC			JScc ea
	else PC+1➞PC

Description: Jump to the subroutine whose location in program memory is given by the instruction’s effective address if the specified condition is true. If the specified condition is true, the address of the instruction immediately following the JScc instruction (PC) and the system status register (SR) are pushed onto the system stack. Program execution then continues at the specified effective address in program memory. If the specified condition is false, the program counter (PC) is incremented, and any extension word is ignored. However, the address register specified in the effective address field is always updated independently of the specified condition. All memory alterable addressing modes may be used for the effective address. A fast short jump addressing mode may also be used. The 12-bit data is zero extended to form the effective address. The term “cc” may specify the following conditions:

	“cc” Mnemonic	Condition
CC (HS)	— carry clear (higher or same)	C=0
CS (LO)	— carry set (lower)	C=1
EC	— extension clear	E=0
EQ	— equal	Z=1
ES	— extension set	E=1
GE	— greater than or equal	N ⊕ V=0
GT	— greater than	Z+(N	⊕ V)=0
LC	— limit clear	L=0	⊕ V)=1
LE	— less than or equal	Z+(N
LS	— limit set	L=1
LT	— less than	N ⊕ V=1
MI	— minus	N=1
NE	— not equal	Z=0	•
NR	— normalized	Z+(U
				E)=1
PL	— plus	N=0	•
NN	— not normalized	Z+(U
				E)=0

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