PROGRAMMING MODEL
MOTOROLA
ADDRESS GENERATION UNIT 4 - 7
4.3.1 Address Register Files (R0 - R3 and R4 - R7)
The eight 16-bit address registers, R0 - R7, can contain addresses or general-purpose
data. The 16-bit address in a selected address register is used in the calculation of the
effective address of an operand. When supporting parallel X and Y data memory moves,
the address registers must be thought of as two separate files, R0 - R3 and R4 - R7. The
contents of an Rn may point directly to data or may be offset. In addition, Rn can be pre-
updated or post-updated according to the addressing mode selected. If an Rn is updated,
modifier registers, Mn, are always used to specify the type of update arithmetic. Offset
registers, Nn, are used for the update-by-offset addressing modes. The address register
modification is performed by one of the two modulo arithmetic units. Most addressing
modes modify the selected address register in a read-modify-write fashion; the address
register is read, its contents are modified by the associated modulo arithmetic unit, and
the register is written with the appropriate output of the modulo arithmetic unit. The form
of address register modification performed by the modulo arithmetic unit is controlled by
the contents of the offset and modifier registers discussed in the following paragraphs. Ad-
dress registers are not affected by a processor reset.
4.3.2 Offset Register Files (N0
-
N3 and N4
-
N7)
The eight 16-bit offset registers, N0 - N7, can contain offset values used to increment/dec-
rement address registers in address register update calculations or can be used for 16-bit
general-purpose storage. For example, the contents of an offset register can be used to
step through a table at some rate (e.g., five locations per step for waveform generation),
or the contents can specify the offset into a table or the base of the table for indexed ad-
dressing. Each address register, Rn, has its own offset register, Nn, associated with it.
*R7
R6
R5
R4
R3
R2
R1
R0
*
*
*
*
*
*
*
23 16 15 0
N7
N6
N5
N4
N3
N2
N1
N0
23 16 15 0
OFFSET REGISTERS
M7
M6
M5
M4
M3
M2
M1
M0
23 16 15 0
MODIFIER REGISTERS
UPPER FILE
LOWER FILE
ADDRESS REGISTERS
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
* Written as don’t care; read as zero
Figure 4-3 AGU Programming Model