Motorola 24-Bit Digital Signal Processor, DSP56000 manual Other Interrupt Sources

EXCEPTION PROCESSING STATE (INTERRUPT PROCESSING)

7.3.3.3 Other Interrupt Sources

Other interrupt sources include the stack error interrupt and trace interrupt (DSP56000/ 56001) which are IPL3 interrupts.

An overflow or underflow of the system stack (SS) causes a stack error interrupt which is vectored to P:$0002 (see SECTION 5 - PROGRAM CONTROL UNIT for additional infor- mation on the stack error flag). Since the stack error is nonrecoverable, a long interrupt should be used to service it. The service routine should not end in an RTI because exe- cuting an RTI instruction “pops” the stack, which has been corrupted.

The DSP56000/56001 includes a facility for instruction-by-instruction tracing as a pro- gram development aid. This trace mode generates a trace exception after each instruc- tion executed (see Figure 7-7), which can be used by a debugger program to monitor the execution of a program. (With members of the DSP56K family other than DSP56000/ 56001, use the OnCE trace mode described in 10.5.)

The trace bit in the SR defines the trace mode. In the trace mode, the processor will gen- erate a trace exception after it executes each instruction. When the processor is servic- ing the trace exception, it expects to encounter a JSR in the trace vector locations, thereby forming a long interrupt routine. The JSR stacks the SR and clears the trace bit to prevent tracing while executing the trace exception service routine. This service rou- tine should end with an RTI instruction, which restores the SR (with the trace bit set) from the SS, and causes the next instruction to be traced. The pipeline must be flushed to allow each sequential instruction to be traced. The tracing facility appends three instruc- tion cycles to the end of each instruction traced (see the three NOP instructions shown in Figure 7-7)to flush the pipeline and allow the next trace interrupt to follow the next sequential interrupt.

During tracing, the processor considers the REP instruction and the instruction being repeated as a single two-word instruction. That is, only after executing the REP instruc- tion and all of the repeats of the next instruction will the trace exception be generated.

Fast interrupts can not be traced because they are uninterruptable. Long interrupts will not be traced unless the processor enters the trace mode in the subroutine because the SR is pushed on the stack and the trace bit is cleared. Tracing is resumed upon returning from a long interrupt because the trace bit is restored when the SR is restored. Interrupts are not likely to occur during tracing because only an interrupt with a higher IPL can interrupt during a trace operation. While executing the program being traced, the trace interrupt will always be pending and will win the interrupt arbitration. During the trace interrupt, the interrupt mask is set to reject interrupts below IPL3.

7 - 22 PROCESSING STATES MOTOROLA