PROGRAM CONTROL UNIT (PCU) ARCHITECTURE
MOTOROLA
PROGRAM CONTROL UNIT 5 - 7
INSTRUCTION
FETCH
LOGIC
INSTRUCTION
FETCH
LOGIC
INSTRUCTION
FETCH
LOGIC
INSTRUCTION FETCH
INSTRUCTION DECODE
INSTRUCTION EXECUTION
I1 I2
I1 I3
I2
I1
I4
I3
I2
I5
I4
I3
PARALLEL
OPERATIONS INITIAL
CONDITIONS
ADDRESS
UPDATE
(AGU) R0=$0005
R4=$0008 R0=5+1
R4=8+1 R0=6+1
R4=9–1 R0=7+1
R4=8+1
INSTRUCTION
EXECUTION
(DATA ALU)
A:
A2=$00
A1=$000066
A0=$000000
X0=$400000
Y1=$000077
A:
A2=$00
A1=$0000A2
A0=$000000
X0=$000005
Y1=$000008
A:
A2=$00
A1=$000000
A0=$000000
X0=$000005
Y1=$000008
A:
A2=$00
A1=$000000
A0=$000050
X0=$000007
Y1=$000008
X MEMORY
AT ADDRESS
$0005
$0006
$0007
DATA
$000005
$000006
$000007
$000005
$000006
$000007
$000005
$000005
$000007
$000005
$000005
$000007
Y MEMORY
AT ADDRESS
$0008
$0009
DATA
$000008
$000009 $000008
$000009 $000008
$0000A2 $000008
$0000A2
Figure 5-3 Three-Stage Pipeline
INSTRUCTION
DECODE
LOGIC
INSTRUCTION
DECODE
LOGIC
INSTRUCTION
DECODE
LOGIC
INSTRUCTION
EXECUTION
LOGIC
INSTRUCTION
EXECUTION
LOGIC
INSTRUCTION
EXECUTION
LOGIC
Instruction/Data Fetch
Instruction Decode
Instruction Execution
PARALLEL PROCESSING OF INSTRUCTIONS
SERIAL EXECUTION OF INSTRUCTIONS
Instruction Cycle 1 Instruction Cycle 2 Instruction Cycle 3 Instruction Cycle 5Instruction Cycle
Instruction Cycle 1 Instruction Cycle 2 Instruction Cycle 3 Instruction Cycle 4Instruction Cycle 5
EXAMPLE PROGRAM SEGMENT
Instruction 1 MACR X0,Y1,A X:(R0)+,X0 Y:(R4)+,Y1
Instruction 2 CLR A X0,X:(R0)+ A,Y:(R4)-
Instruction 3 MAC X0,Y1,A X:(R0)+,X0 Y:(R4)+,Y1
SEQUENCE OF OPERATIONS
INSTRUCTION
FETCH
LOGIC
INSTRUCTION
FETCH
LOGIC
INSTRUCTION
DECODE
LOGIC
5
4
4
3
3
3
2
2
2
1
1
1
EXECUTION OF EXAMPLE PROGRAM