Motorola 24-Bit Digital Signal Processor, DSP56000 manual OnCE Controller and Serial Interface

OnCE CONTROLLER AND SERIAL INTERFACE

10.2.4 Debug Request Input (DR)

The debug request input (DR) allows the user to enter the debug mode of operation from the external command controller. When DR is asserted, it causes the DSP56K to finish the current instruction being executed, save the instruction pipeline information, enter the debug mode, and wait for commands to be entered from the DSI line. While in debug mode, the DR pin lets the user reset the OnCE controller by asserting it and deasserting it after receiving acknowledge. It may be necessary to reset the OnCE controller in cases where synchronization between the OnCE controller and external circuitry is lost. DR must be deasserted after the OnCE responds with an acknowledge on the DSO pin and before sending the first OnCE command. Asserting DR will cause the chip to exit the STOP or WAIT state.

10.3OnCE CONTROLLER AND SERIAL INTERFACE

The OnCE Controller and Serial Interface contains the following blocks: OnCE command register, bit counter, OnCE decoder, and the status/control register. Figure 10-3illustrates a block diagram of the OnCE controller and serial interface

10.3.1 OnCE Command Register (OCR)

The OCR is an 8-bit shift register that receives its serial data from the DSI pin. It holds the 8-bit commands to be used as input for the OnCE Decoder. The Command Register is shown in Figure 10-4.

ISBKPT

ISTRACE

ISDR

ISDEBUG

ISSWDBG

OnCE COMMAND REGISTER	. DSI
	. DSCK

	BIT 7	.
OnCE DECODER	BIT COUNTER
	BIT 23

.	.	STATUS AND CONTROL
		REGISTER
		DSO

REG READ REG WRITE MODE SELECT

Figure 10-3 OnCE Controller and Serial Interface

MOTOROLA ON-CHIP EMULATION (OnCE) 10 - 7