ORIGIN OF DIGITAL SIGNAL PROCESSING
1- 6 DSP56K FAMILY INTRODUCTION
MOTOROLA
The DSP56K family is not designed for a particular application but is designed to execute
commonly used DSP benchmarks in a minimum time for a single-multiplier architecture.
For example, a cascaded, 2nd-order, four-coefficient infinite impulse response (IIR) bi-
quad section has four multiplies for each section. For that algorithm, the theoretical
minimum number of operations for a single-multiplier architecture is four per section. Ta-
ble 1-1 shows a list of benchmarks with the number of instruction cycles a DSP56K chip
uses compared to the number of multiplies the algorithm requires.
These benchmarks and others are used independently or in combination to implement
functions whose characteristics are controlled by the coefficients of the benchmarks being
executed. Useful functions using these and other benchmarks include the following:
Benchmark Number of Cycles Number of
Algorithm
Multiplies
Real Multiply 3 1
N Real Multiplies 2N N
Real Update 4 1
N Real Updates 2N N
N Term Real Convolution (FIR) N N
N Term Real * Complex Convolution 2N N
Complex Multiply 6 4
N Complex Multiplies 4N N
Complex Update 7 4
N Complex Updates 4N 4N
N Term Complex Convolution (FIR) 4N 4N
Nth - Order Power Series 2N 2N
2nd - Order Real Biquad Filter 7 4
N Cascaded 2nd - Order Biquads 4N 4N
N Radix Two FFT Butterflies 6N 4N
Table 1-1 Benchmark Summary in Instruction Cycles