Motorola 24-Bit Digital Signal Processor Loop Flag Bit, Operating Mode Register, System Stack

PROGRAMMING MODEL

23 8 7 6 5 4 3 2 1 0

*

*

SD

*

MC YD DE MB MA

OPERATING MODE A, B

DATA ROM ENABLE

INTERNAL Y MEMORY DISABLE

OPERATING MODE C

RESERVED

STOP DELAY

RESERVED

RESERVED

Figure 5-6 OMR Format

tions. The DSP56K software simulator accurately shows how the MPY, MAC, and other Data ALU instructions operate while the processor is in the double precision multiply mode.

5.4.2.14Loop Flag (Bit 15)

The loop flag (LF) bit is set when a program loop is in progress. It detects the end of a program loop. The LF is the only SR bit that is restored when a program loop is termi- nated. Stacking and restoring the LF when initiating and exiting a program loop, respec- tively, allow the nesting of program loops. At the start of a long interrupt service routine, the SR (including the LF) is pushed on the SS and the SR LF is cleared. When returning from the long interrupt with an RTI instruction, the SS is pulled and the LF is restored. During a processor reset, the LF is cleared.

5.4.3 Operating Mode Register

The OMR is a 24-bit register (only six bits are defined) that sets the current operating mode of the processor. Each chip in the DSP56K family of processors has its own set of operating modes which determine the memory maps for program and data memories, and the startup procedure that occurs when the chip leaves the reset state. The OMR bits are only affected by processor reset and by the ANDI, ORI, and MOVEC instructions, which directly reference the OMR.

The OMR format with all of its defined bits is shown in Figure 5-6.For product-specific OMR bit definitions, see the individual chip’s user manual for details on its respective op- erating modes.

5.4.4 System Stack

The SS is a separate 15X32-bit internal memory divided into two banks, the SSH and the

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