Motorola 24-Bit Digital Signal Processor, DSP56000 Hardware Interrupt Sources, Starting Address

EXCEPTION PROCESSING STATE (INTERRUPT PROCESSING)

Table 7-6 Interrupt Sources

Interrupt	IPL		Interrupt Source
Starting Address
$0000	3	Hardware
				RESET
$0002	3	Stack Error
$0004	3	Trace
$0006	3	SWI
$0008	0 - 2
		IRQA
$000A	0 - 2
		IRQB

:: Vectors available for peripherals

$001E 3 NMI

:: Vectors available for peripherals

$003E 3 Illegal Instruction

When an interrupt occurs, the instruction at the interrupt starting address is fetched first. Because the program flow is directed to a different starting address for each interrupt, the interrupt structure of the DSP56K can be described as “vectored”. A vectored inter- rupt structure has low execution overhead. If it is known beforehand that certain inter- rupts will not be used, those interrupt vector locations can be used for program or data storage.

7.3.3.1 Hardware Interrupt Sources

There are two types of hardware interrupts in the DSP56K: internal and external. The internal interrupt sources include all of the on-chip peripheral devices. For further infor- mation on a device’s internal interrupt sources, see the device’s individual User’s Man- ual.

The external hardware interrupt sources are the RESET, NMI, IRQA, and IRQB pins on the program interrupt controller in the Program Control Unit.

The level sensitive RESET interrupt is the highest priority interrupt with an IPL of 3. IRQA and IRQB can be programmed to one of three priority levels: 0, 1, or 2 - all of which are maskable. IRQA and IRQB have independent enable control and can be programmed to be level sensitive or edge sensitive. Since level-sensitive interrupts will not be cleared automatically when they are serviced, they must be cleared by other means to prevent multiple interrupts. Edge-sensitive interrupts are latched as pending on the high-to-low transition of the interrupt input and are automatically cleared when the interrupt is ser- viced.

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