INSTRUCTION SET DESCRIPTIONS

NORM

Normalize Accumulator Iteration NORM

cess in the R3 address register. A negative value reflects the number of left shifts performed; a positive value reflects the number of right shifts performed during the nor- malization process.

Condition Codes:

15

14

 

13

12

11

10

9

8

7

6

 

5

4

3

2

1

0

LF

DM

T

**

 

S1

S0

 

I1

I0

S

L

E

U

 

N

Z

 

V

C

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

MR

 

 

 

 

 

 

 

 

 

 

 

CCR

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

L — Set if overflow has occurred in A or B result

E — Set if the signed integer portion of A or B result is in use

U — Set if A or B result is unnormalized

N — Set if bit 55 of A or B result is set

Z — Set if A or B result equals zero

V — Set if bit 55 is changed as a result of a left shift

Note: The definitions of the E and U bits vary according to the scaling mode being used. Refer to Section A.5 CONDITION CODE COMPUTATION for complete details.

Instruction Format:

NORM Rn,D

Opcode:

23

16

15

8

7

0

0 0 0 0 0 0 0 1

1 1 0 1 1 R R R 0 0 0 1 d 1 0 1

Instruction Fields:

 

 

D d

Rn

R R R

A

0

Rn

n n n

B

1

 

 

where “nnn” = Rn number

Timing: 2 oscillator clock cycles

Memory: 1 program word

MOTOROLA

INSTRUCTION SET DETAILS

A - 241

Page 510
Image 510
Motorola DSP56000, 24-Bit Digital Signal Processor manual Normalize Accumulator Iteration Norm, Condition Codes