Motorola DSP56000 manual Loss of Lock, Stop Processing State, Ckout Considerations

PLL OPERATION CONSIDERATIONS

chip clock. (Here, T3 is equal to the phase described by the new divide factor plus the time required to wait for a synchronizing pulse, which is less than 1.5ETc.) For MF>4, such synchronization is not guaranteed and the instruction cycle is not lengthened.

If the DF0-DF3 bits are changed by the same instruction that changes the MF0-MF11 bits, the LPD divider factor changes before the detection of the change in the multiplica- tion factor. This means that the detection of loss of lock will occur after the LPD has started dividing by the new division factor.

9.4.6Loss of Lock

The PLL distinguishes between cases where MF>4 and cases where MF≤4. If MF≤4, the PLL will detect loss of lock if a skew of 2.5 to 4.5 ns develops between the two clock inputs to the phase detector.

If MF>4, the PLL will detect loss of lock when there is a discrepancy of one clock cycle between the two clock inputs to the phase detector. When either of these two conditions occurs, the following also occur:

1.PLOCK will be deasserted, indicating that loss of lock condition has occurred.

2.The PLL will re-acquire the proper phase/frequency. When lock occurs, PLOCK will be asserted.

9.4.7STOP Processing State

If the PSTP bit is cleared, executing the STOP instruction will disable the on-chip crystal oscillator and the PLL. In this state the chip consumes the least possible power. When recovering from the STOP state, the recovery time will be 16 or 64k external clock cycles (according to bit 6 in the Operating Mode Register) plus the time needed for the PLL to achieve lock.

If the PSTP bit is set, executing the STOP instruction will leave the on-chip crystal oscil- lator (if XTLD=0) and the PLL loop (if PEN=1) operating, but will disable the clock to the LPD and the rest of the DSP. When recovering from the STOP state, the recovery time will be only three clock cycles.

9.4.8CKOUT Considerations

The CKOUT clock output is held high while disabled, which is also while the COD0-COD1 bits are set. If the CKOUT clock output is low at the moment the COD0-COD1 bits are set, then the CKOUT clock output will complete the low cycle and then be disabled high. If the programmer re-enables the CKOUT clock output before it reaches the high logic level dur- ing the disabling process, the CKOUT operation will be unaffected.

MOTOROLA PLL CLOCK OSCILLATOR 9 - 13