Motorola 24-Bit Digital Signal Processor manual Interrupt Arbitration, Interrupt Instruction Fetch

EXCEPTION PROCESSING STATE (INTERRUPT PROCESSING)

7.3.4 Interrupt Arbitration

Interrupt arbitration and control, which occurs concurrently with the fetch-decode-exe- cute cycle, takes two instruction cycles. External interrupts are internally synchronized with the processor clock before their interrupt-pending flags are set. Each external and internal interrupt has its own flag. After each instruction is executed, the DSP arbitrates all interrupts. During arbitration, each interrupt’s IPL is compared with the interrupt mask in the SR, and the interrupt is either allowed or disallowed. The remaining interrupts are prioritized according to the IPLs shown in Table 7-5,and the highest priority interrupt is chosen. The interrupt vector is then calculated so that the program interrupt controller can fetch the first interrupt instruction.

Interrupts from a given source are not buffered. The processor won’t arbitrate a new interrupt from the same source until after it fetches the second interrupt vector of the cur- rent interrupt.

The internal interrupt acknowledge signal clears the edge-triggered interrupt flags and the internal latches of the NMI, SWI, and trace interrupts. The stack error bit in the stack pointer register is “sticky” and requires a “MOVE” or a bit clear operation directly on the stack pointer register. Some peripheral interrupts may also be cleared by the internal interrupt acknowledge signal, as defined in their specifications. Peripheral interrupt requests that need a read/write action to some register do not receive the internal inter- rupt acknowledge signal, and they will remain pending until their registers are read/writ- ten. Further, level-triggered interrupts will not be cleared. The acknowledge signal will be generated after the interrupt vectors have been generated, not before.

7.3.5 Interrupt Instruction Fetch

The interrupt controller generates an interrupt instruction fetch address, which points to the first instruction word of a two-word interrupt routine. This address is used for the next instruction fetch, instead of the contents of the PC, and the interrupt instruction fetch address +1 is used for the subsequent instruction fetch. While the interrupt instructions are being fetched, the PC cannot be updated. After the two interrupt words have been fetched, the PC is used for any subsequent instruction fetches.

After both interrupt vectors have been fetched, they are guaranteed to be executed. This is true even if the instruction that is currently being executed is a change-of-flow instruc- tion (i.e., JMP, JSR, etc.) that would normally ignore the instructions in the pipe. After the interrupt instruction fetch, the PC will point to the instruction that would have been fetched if the interrupt instructions had not been inserted.

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