Motorola 24-Bit Digital Signal Processor Address Register Indirect Postdecrement by Offset Nn

ADDRESSING

EXAMPLE: MOVE X:(R4)–N4,A0

			BEFORE EXECUTION
	A2		A1				A0
55	48 47		24	23				0
0 F		7 4 1 0 5 A		3 F A 6 B 0
7	0 23		0	23				0
				23		X MEMORY		0
			$7706	$ 5 0 5			0 5	0
			$7703	X X X			X X	X
				15				0
							$7706
						R4
				15				0
							$0003
						N4
				15				0
							$FFFF
					M4

Assembler Syntax: (Rn)–Nn

Memory Spaces: P:, X:, Y:, L:

Additional Instruction Execution Time (Clocks): 0

Additional Effective Address Words: 0

			AFTER EXECUTION
A2			A1			A0
55	48 47		24 23				0
0	F	7	4 1 0 5 A	5 0 5 0			5 0
7	0 23		0 23				0
					X MEMORY
			23				0

$7706 $ 5 0 5 0 5 0

$7703	X	X	X	X	X	X
			15			0
		R4		$7703
			15			0
		N4		$0003
			15			0
		M4		$FFFF

Figure 4-8 Address Register Indirect — Postdecrement by Offset Nn

move.

4.4.2Address Modifier Arithmetic Types

The address ALU supports linear, modulo, and reverse-carry arithmetic for all address register indirect modes. These arithmetic types easily allow the creation of data structures in memory for FIFOs (queues), delay lines, circular buffers, stacks, and bit-reversed FFT buffers.

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