Motorola 24-Bit Digital Signal Processor ABS a A,B, #$Fe,Ccr, DIV X0,A, Tfr A,B, JPL Savequo

INSTRUCTION DESCRIPTIONS

DIVDivide InterationDIV

Example: (4-Quadrant division, 24-bit signed quotient, 48-bit signed remainder)

	ABS A A,B		;make dividend positive, copy A1 to B1
	EOR X0,B B,X:$0		;save rem. sign in X:$0, quo. sign in N
	AND #$FE,CCR		;clear carry bit C (quotient sign bit)
	REP #$18		;form a 24-bit quotient
	DIV X0,A		;form quotient in A0, remainder in A1
	TFR A,B		;save quotient and remainder in B1,B0
	JPL SAVEQUO		;go to SAVEQUO if quotient is positive
	NEG B		;complement quotient if N bit set
SAVEQUO TFR X0,B B0,X1			;save quo. in X1, get signed divisor
	ABS B		;get absolute value of signed divisor
	ADD A,B		;restore remainder in B1
	JCLR #23,X:$0,DONE		;go to DONE if remainder is positive
	MOVE #$0,B0		;clear LS 24 bits of B
	NEG B		;complement remainder if negative
DONE	. . . . . . .
		Before Execution	After Execution

A

X0

X1

B

$00:0E66D7:F2832C

$123456

$000000

$00:000000:000000

A

X0

X1

B

$FF:EDCCAA:654321

$123456

$654321

$00:000100:654321

Explanation of Example: Prior to execution, the 56-bit A accumulator contains the 56- bit, sign-extended fractional dividend D (D=$00.0E66D7:F2832C=0.112513535894635 approx.) and the 24-bit X0 register contains the 24-bit, signed fractional divisor S (S=$123456=0.142222166061401). Since D<S, the execution of the previous divide routine stores the correct 24-bit signed quotient in the 24-bit X1 register (A/ X0=0.79111111164093=$654321=X1). The partial remainder is restored by reversing the last DIV operation and adding back the absolute value of the signed divisor in X0 to the partial remainder in A1. This produces the correct LS 24 bits of the 48-bit signed remained in the 24-bit B1 register. Note that the remainder is really a 48-bit value which has 24 bits of precision. Thus, the correct 48-bit remainder is $000000:000100 which equals 0.0000000000018190 approximately.

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