Motorola 24-Bit Digital Signal Processor, DSP56000 manual Shift Left and Add Accumulators

INSTRUCTION DESCRIPTIONS

	ADDL	Shift Left and Add Accumulators		ADDL
Operation:			Assembler Syntax:
	S+2∗D➞D (parallel move)		ADDL S,D (parallel move)

Description: Add the source operand S to two times the destination operand D and store the result in the destination accumulator. The destination operand D is arithmeti- cally shifted one bit to the left, and a zero is shifted into the LS bit of D prior to the addi- tion operation. The carry bit is set correctly if the source operand does not overflow as a result of the left shift operation. The overflow bit may be set as a result of either the shift- ing or addition operation (or both). This instruction is useful for efficient divide and deci- mation in time (DIT) FFT algorithms.

Example:

:

ADDL A,B #$0,R0

:

		Before Execution
A
	$00:000000:000123

;A+2∗B➞B, set up addr. reg. R0

After Execution

A$00:000000:000123

B

$00:005000:000000

B

$00:00A000:000123

Explanation of Example: Prior to execution, the 56-bit accumulator contains the value $00:000000:000123, and the 56-bit B accumulator contains the value $00:005000:000000. The ADDL A,B instruction adds two times the value in the B accu- mulator to the value in the A accumulator and stores the 56-bit result in the B accumula- tor.

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