Motorola 24-Bit Digital Signal Processor, DSP56000 manual Compare

INSTRUCTION DESCRIPTIONS

CMP Compare CMP

Operation:	Assembler Syntax:
S2 – S1(parallel move)	CMP S1, S2 (parallel move)

Description: Subtract the source one operand, S1, from the source two accumulator, S2, and update the condition code register. The result of the subtraction operation is not stored.

Note: This instruction subtracts 56-bit operands. When a word is specified as S1, it is sign extended and zero filled to form a valid 56-bit operand. For the carry to be set cor- rectly as a result of the subtraction, S2 must be properly sign extended. S2 can be improperly sign extended by writing A1 or B1 explicitly prior to executing the compare so that A2 or B2, respectively, may not represent the correct sign extension. This note par- ticularly applies to the case where it is extended to compare 24-bit operands such as X0 with A1.

Example:

		:
CMP		Y0,B		X0,X:(R6)+N6
		:
				Before Execution
	B
			$00:000020:000000

Y1,Y:(R0)– ;comp. Y0 and B, save X0, Y1

After Execution

B $00:000020:000000

Y0

$000024

Y0

$000024

SR

$0300

SR

$0319

Explanation of Example: Prior to execution, the 56-bit B accumulator contains the value $00:000020:000000 and the 24-bit Y0 register contains the value $000024. The execution of the CMP Y0,B instruction automatically appends the 24-bit value in the Y0 register with 24 LS zeros, sign extends the resulting 48-bit long word to 56 bits, subtracts the result from the 56-bit B accumulator and updates the condition code register.

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