Motorola 24-Bit Digital Signal Processor, DSP56000 manual Register to Register Data Move

INSTRUCTION DESCRIPTIONS

R		Register to Register Data Move
Operation:		Assembler Syntax:
(	); S➞D	(	) S,D

R

where ( . . . . . ) refers to any arithmetic or logical instruction which allows parallel moves.

Description: Move the source register S to the destination register D.

If the arithmetic or logical opcode-operand portion of the instruction specifies a given destination accumulator, that same accumulator or portion of that accumulator may not be specified as a destination D in the parallel data bus move operation. Thus, if the opcode-operand portion of the instruction specifies the 56-bit A accumulator as its desti- nation, the parallel data bus move portion of the instruction may not specify A0, A1, A2, or A as its destination D. Similarly, if the opcode-operand portion of the instruction speci- fies the 56-bit B accumulator as its destination, the parallel data bus move portion of the instruction may not specify B0, B1, B2, or B as its destination D. That is, duplicate des- tinations are NOT allowed within the same instruction.

If the opcode-operand portion of the instruction specifies a given source or destination register, that same register or portion of that register may be used as a source S in the parallel data bus move operation. This allows data to be moved in the same instruction in which it is being used as a source operand by a data ALU operation. That is, duplicate sources are allowed within the same instruction.

When a 24-bit source operand is moved into a 16-bit destination register, the 16 LS bits of the 24-bit source operand are stored in the 16-bit destination register. When a 16-bit source operand is moved into a 24-bit destination register, the 16 LS bits of the destina- tion register are loaded with the contents of the 16-bit source operand, and the eight MS bits of the 24-bit destination register are zeroed.

Note: The MOVE A,B operation will result in a 24-bit positive or negative saturation con- stant being stored in the B1 portion of the B accumulator if the signed integer portion of the A accumulator is in use.

Note: Due to instruction pipelining, if an AGU register (Mn, Nn, or Rn) is directly changed with this instruction, the new contents may not be available for use until the second fol- lowing instruction. See the restrictions discussed in A.9.6 - R, N, and M Register Restric- tions on page A-310.

A - 168 INSTRUCTION SET DETAILS MOTOROLA