Motorola 24-Bit Digital Signal Processor manual At LA-2, LA-1, and LA, Andi MR, Ori Mr, At LA-1

INSTRUCTION DESCRIPTIONS

DO

Start Hardware Loop

DO

ing the last instruction in the DO loop. Note that LF is the only bit in the status register (SR) that is restored after a hardware DO loop has been exited.

Note: The loop flag (LF) is cleared by a hardware reset.

Restrictions: The “end-of-loop” comparison previously described actually occurs at instruction fetch time. That is, LA is being compared with PC when the instruction at LA– 2 is being executed. Therefore, instructions which access the program controller regis- ters and/or change program flow cannot be used in locations LA–2, LA–1, or LA.

Proper DO loop operation is not guaranteed if an instruction starting at address LA–2, LA–1, or LA specifies one of the program controller registers SR, SP, SSL, LA, LC, or (implicitly) PC as a destination register. Similarly, the SSH program controller register may not be specified as a source or destination register in an instruction starting at address LA–2, LA–1, or LA. Additionally, the SSH register cannot be specified as a source register in the DO instruction itself and LA cannot be used as a target for jumps to subroutine (i.e., JSR, JScc, JSSET, or JSCLR to LA). A DO instruction cannot be repeated using the REP instruction.

The following instructions cannot begin at the indicated position(s) near the end of a DO loop:

At LA–2, LA–1, and LA	DO
	MOVEC from SSH
	MOVEM from SSH
	MOVEP from SSH
	MOVEC to LA, LC, SR, SP, SSH, or SSL
	MOVEM to LA, LC, SR, SP, SSH, or SSL
	MOVEP to LA, LC, SR, SP, SSH, or SSL
	ANDI MR
	ORI MR
	Two-word instructions which read LC, SP, or SSL
At LA–1	Single-word instructions (except REP) which read LC,
	SP, or SSL, JCLR, JSET, two-word JMP, two-word Jcc

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