Motorola 24-Bit Digital Signal Processor, DSP56000 manual Shift Left and Subtract Accumulators

INSTRUCTION DESCRIPTIONS

	SUBL	Shift Left and Subtract Accumulators		SUBL
Operation:			Assembler Syntax:
	2∗D–S ➞ D (parallel move)		SUBL S,D (parallel move)

Description: Subtract the source operand S from two times the destination operand D and store the result in the destination accumulator. The destination operand D is arith- metically shifted one bit to the left, and a zero is shifted into the LS bit of D prior to the subtraction operation. The carry bit is set correctly if the source operand does not over- flow as a result of the left shift operation. The overflow bit may be set as a result of either the shifting or subtraction operation (or both). This instruction is useful for efficient divide and decimation in time (DIT) FFT algorithms.

Example:

:

SUBL A,B Y:(R5+N5),R7

	:
			Before Execution
A
		$00:004000:000000

;2∗B–A ➞ B, load R7, no R5 update

		After Execution
A
	$00:004000:000000

B$00:005000:000000

B

$00:006000:000000

Explanation of Example: Prior to execution, the 56-bit A accumulator contains the value $00:004000:000000, and the 56-bit B accumulator contains the value $00:005000:000000. The SUBL A,B instruction subtracts the value in the A accumulator from two times the value in the B accumulator and stores the 56-bit result in the B accu- mulator.

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