PLL CLOCK OSCILLATOR INTRODUCTION
MOTOROLA
PLL CLOCK OSCILLATOR 9 - 3
9.1 PLL CLOCK OSCILLATOR INTRODUCTION
The DSP56K family of processors (with the exception of the DSP56000 and DSP56001)
features a PLL (phase-locked loop) clock oscillator in its central processing module,
shown in Figure 9-2. The PLL allows the processor to operate at a high internal clock fre-
quency using a low frequency clock input, a feature which offers two immediate benefits.
Lower frequency clock inputs reduce the overall electromagnetic interference generated
by a system, and the ability to oscillate at different frequencies reduces costs by eliminat-
ing the need to add additional oscillators to a system.
The PLL performs frequency multiplication to allow the processor to use almost any
available external system clock for full speed operation, while also supplying an output
clock synchronized to a synthesized internal core clock. It also improves the synchro-
nous timing of the processor’s external memory port, significantly reducing the timing
skew between EXTAL and the internal chip phases. The PLL is unusual in that it pro-
vides a low power divider on its output, which can reduce or restore the chip operating
frequency without losing the PLL lock
A DSP56K processor uses a four-phase clock for instruction execution which runs at the
instruction execution rate. It can accept an external clock through the EXTAL input, or it
can run on an internal oscillator, bypassing the PLL function, when the user connects an
external crystal between XTAL and EXTAL. (The PLL need not be disabled when the
processor accepts an external clock.)
9.2 PLL COMPONENTS
The PLL block diagram is shown below in Figure 9-1. The components of the PLL are de-
scribed in the following sections.
DIVIDER OUT
EXTAL
VCO OUT
MF0-MF11
DF0-DF3
Phase
Detector
(PD)
Charge
Pump
Loop
Filter
Voltage
Controlled
Oscillator
(VCO)
Low
Power
Divider
20 to 215
Multiplication
Factor
1 to 4096
Figure 9-1 PLL Block Diagram
Frequency
Multiplier