Motorola 24-Bit Digital Signal Processor, DSP56000 manual Round Accumulator

INSTRUCTION DESCRIPTIONS

	RND	Round Accumulator	RND
Operation:		Assembler Syntax:
	D+r ➞ D (parallel move)	RND D (parallel move)

Description: Round the 56-bit value in the specified destination operand D and store the result in the MSP portion of the destination accumulator (A1 or B1). This instruction uses a convergent rounding technique. The contribution of the LS bits of the result (A0 and B0) is rounded into the upper portion of the result (A1 or B1) by adding a rounding con- stant to the LS bits of the result. The MSP portion of the destination accumulator con- tains the rounded result which may be read out to the data buses.

The value of the rounding constant added is determined by the scaling mode bits S0 and S1 in the system status register (SR). A “1” is added in the rounding position as shown below:

			Rounding			Rounding Constant
S1	S0	Scaling Mode	Position	55 - 25		24	23	22	21 - 0
0	0	No Scaling	23	0. . . .	0	0	1	0	0. . . .	0
0	1	Scale Down	24	0. . . .	0	1	0	0	0. . . .	0
1	0	Scale Up	22	0. . . .	0	0	0	1	0. . . .	0

Normal or “standard’’ rounding consists of adding a rounding constant to a given number of LS bits of a value to produce a rounded result. The rounding constant depends on the scaling mode being used as previously shown. Unfortunately, when using a twos-complement data representation, this process introduces a positive bias in the statistical distribution of the roundoff error.

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