Motorola DSP56000, 24-Bit Digital Signal Processor Data ALU Programming Model, Data ALU Summary

DATA ALU PROGRAMMING MODEL

3.5DATA ALU PROGRAMMING MODEL

The Data ALU features 24-bit input/output data registers that can be concatenated to ac- commodate 48-bit data and two 56-bit accumulators, which are segmented into three 24- bit pieces that can be transferred over the buses. Figure 3-14illustrates how the registers in the programming model are grouped.

DATA ALU

INPUT REGISTERS

X Y

47		0
	X1	X0
23	0 23	0

47		0
	Y1	Y0
23	0 23	0

DATA ALU

ACCUMULATOR REGISTERS

A B

	55						0
*		A2			A1		A0
23	8 7		0	23	0	23	0

*Read as sign extension bits, written as don’t care.

			55					0
*				B2		B1		B0
23	8	7		0 23	0	23	0

Figure 3-14 DSP56K Programming Model

3.6DATA ALU SUMMARY

The Data ALU performs arithmetic operations involving multiply and accumulate opera- tions. It executes all instructions in one machine cycle and is not pipelined. The two 24-bit numbers being multiplied can come from the X registers (X0 or X1) or Y registers (Y0 or Y1). After multiplication, they are added (or subtracted) with one of the 56-bit accumula- tors and can be convergently rounded to 24 bits. The convergent-rounding forcing function detects the $800000 condition in the LSP and makes the correction as neces- sary. The final result is then stored in one of the accumulators as a valid 56-bit number. The condition code bits are set based on the rounded output of the logic unit.

MOTOROLA DATA ARITHMETIC LOGIC UNIT 3 - 19