Motorola DSP56000, 24-Bit Digital Signal Processor manual + yn 1wn-1 Ai1 bi1

BENCHMARK PROGRAMS

page 132,66,0,6 opt rc

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;Motorola Austin DSP Operation June 30, 1988

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;DSP56000/1

;8-pole 4-multiply cascaded canonic IIR filter ;File name: 4-56.asm ;**********************************************************************************************************************

;Maximum sample rate: 410.0 kHz at 20.5 MHz/540.0 kHz at 27.0 MHz

;Memory Size: Prog: 6+10 words; Data: 4(2+4) words

;Number of clock cycles: 50 (25 instruction cycles)

;Clock Frequency: 20.5 MHz/27.0 MHz

;Instruction cycle time: 97.5 ns/74.1 ns ;**********************************************************************************************************************

;This IIR filter reads the input sample

;from the memory location Y:input

;and writes the filtered output sample

;to the memory location Y:output

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;The samples are stored in the X memory

;The coefficients are stored in the Y memory

;The equations of the filter are:

;	w(n)=	x(n)-ai1*w(n-1)-ai2*w(n-2)
;	y(n)=	w(n)+bi1*w(n-1)+bi2*w(n-2)

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;x(n)

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( - )

w(n)

( + ) y(n)

z-1w(n-1)

ai1 bi1

z-1 w(n-2)

ai2 bi2

Figure B 3 8 Pole 4 Multiply Cascaded Canonic IIR Filter (Sheet 1 of 2) Figure B-5 Real Input FFT Based on Glenn Bergland Algorithm (Sheet 3 of 8)

B - 14 BENCHMARK PROGRAMS MOTOROLA