SECTION CONTENTS

SECTION 5.1 PROGRAM CONTROL UNIT

3

SECTION 5.2 OVERVIEW

3

SECTION 5.3 PROGRAM CONTROL UNIT (PCU) ARCHITECTURE

5

5.3.1 Program Decode Controller

5

5.3.2 Program Address Generator (PAG)

5

5.3.3 Program Interrupt Controller

6

5.3.4 Instruction Pipeline Format

6

SECTION 5.4 PROGRAMMING MODEL

8

5.4.1 Program Counter

8

5.4.2 Status Register

9

5.4.2.1 Carry (Bit 0)

10

5.4.2.2 Overflow (Bit 1)

10

5.4.2.3 Zero (Bit 2)

10

5.4.2.4 Negative (Bit 3)

10

5.4.2.5 Unnormalized (Bit 4)

10

5.4.2.6 Extension (Bit 5)

11

5.4.2.7 Limit (Bit 6)

11

5.4.2.8 Scaling Bit (Bit 7)

11

5.4.2.9 Interrupt Masks (Bits 8 and 9)

12

5.4.2.10 Scaling Mode (Bits 10 and 11)

12

5.4.2.11 Reserved Status (Bit 12)

13

5.4.2.12 Trace Mode (Bit 13)

13

5.4.2.13 Double Precision Multiply Mode (Bit 14)

13

5.4.2.14 Loop Flag (Bit 15)

13

5.4.3 Operating Mode Register

14

5.4.4 System Stack

14

5.4.5 Stack Pointer Register

15

5.4.5.1 Stack Pointer (Bits 0–3)

16

5.4.5.2 Stack Error Flag (Bit 4)

16

5.4.5.3 Underflow Flag (Bit 5)

16

5.4.5.4 Reserved Stack Pointer Registration (Bits 6–23)

17

5.4.6 Loop Address Register

17

5.4.7 Loop Counter Register

17

5.4.8 Programming Model Summary

17

5 - 2

PROGRAM CONTROL UNIT

MOTOROLA

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Motorola 24-Bit Digital Signal Processor, DSP56000 manual Programming Model, Program Control Unit Motorola