Motorola DSP56000 manual Serial Protocol Description, PAB Fifo, OnCE Commands

SERIAL PROTOCOL DESCRIPTION

This register is not affected by the operations performed during the debug mode.

10.8.3 PAB FIFO

The PAB FIFO stores the addresses of the last five instructions that were executed. The FIFO is implemented as a circular buffer containing five 16-bit registers and one 3-bit counter. All the registers have the same address but any read access to the FIFO address will cause the counter to increment, making it point to the next FIFO register. The registers are serially available to the external command controller through their common FIFO ad- dress. Figure 10-9shows the block diagram of the PAB FIFO. The FIFO is not affected by the operations performed during the debug mode except for the FIFO pointer incre- ment when reading the FIFO. When entering the debug mode, the FIFO counter will be pointing to the FIFO register containing the address of the oldest of the five executed in- structions. The first FIFO read will obtain the oldest address and the following FIFO reads will get the other addresses from the oldest to the newest (the order of execution).

To ensure FIFO coherence, a complete set of five reads of the FIFO must be performed because each read increments the FIFO pointer, thus making it point to the next location. After five reads the pointer will point to the same location it pointed to before starting the read procedure.

10.9SERIAL PROTOCOL DESCRIPTION

The following protocol permits an efficient means of communication between the OnCE’s external command controller and the DSP56K chip. Before starting any debugging activ- ity, the external command controller must wait for an acknowledge on the DSO line, indi- cating that the chip has entered the debug mode. The external command controller com- municates with the chip by sending 8-bit commands that may be accompanied by 24 bits of data. Both commands and data are sent or received most significant bit first. After send- ing a command, the external command controller must wait for the processor to acknowl- edge execution of the command before it may send a new command.

When accessing OnCE 16-bit registers, the register contents appear in the 16 most sig- nificant bits in the 24-bit data field, and the 8 least significant bits are zeroed.

10.9.1 OnCE Commands

The OnCE commands may be classified as follows:

•read commands (when the chip will deliver the required data).

•write commands (when the chip will receive data and write the data in one of the OnCE registers).

•commands that do not have data transfers associated with them.

The commands are 8 bits long and have the format shown in Figure 10-4.

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