Motorola 24-Bit Digital Signal Processor, DSP56000 Wait Processing State, Wait Instruction Timing

WAIT PROCESSING STATE

7.5WAIT PROCESSING STATE

The WAIT instruction brings the processor into the wait processing state which is one of two low power-consumption states. Asserting the OnCE’s debug request pin releases the DSP from the wait state. In the wait state, the internal clock is disabled from all inter- nal circuitry except the internal peripherals. All internal processing is halted until an unmasked interrupt occurs, the Debug Request pin of the OnCE is asserted, or the DSP is reset.

Figure 7-15shows a WAIT instruction being fetched, decoded, and executed. It is fetched as n3 in this example and, during decode, is recognized as a WAIT instruction. The following instruction (n4) is aborted, and the internal clock is disabled from all inter- nal circuitry except the internal peripherals. The processor stays in this state until an interrupt or reset is recognized. The response time is variable due to the timing of the interrupt with respect to the internal clock. Figure 7-15shows the result of a fast interrupt bringing the processor out of the wait state. The two appropriate interrupt vectors are fetched and put in the instruction pipe. The next instruction fetched is n4, which had been aborted earlier. Instruction execution proceeds normally from this point.

INTERRUPT SYNCHRONIZED AND

RECOGNIZED AS PENDING

	INTERRUPT CONTROL CYCLE 1					i
	INTERRUPT CONTROL CYCLE 2						i
	FETCH	n3	n4	—				ii1	ii2	n4	n5
	DECODE	n2	WAIT	—					ii1	ii2	n4
	EXECUTE	n1	n2	WAIT						ii1	ii2
	INSTRUCTION CYCLE COUNT	1	2	3	4	5	6	7	8	9	10
i	= INTERRUPT

ii	= INTERRUPT INSTRUCTION WORD
		ONLY INTERNAL PERIPHERALS
n	= NORMAL INSTRUCTION WORD
		RECEIVE CLOCK

Figure 7-15 Wait Instruction Timing

Figure 7-16shows an example of the WAIT instruction being executed at the same time that an interrupt is pending. Instruction n4 is aborted as before. The WAIT instruction causes a five-instruction-cycle delay from the time it is decoded, after which the interrupt is processed normally. The internal clocks are not turned off, and the net effect is that of executing eight NOP instructions between the execution of n2 and ii1.

7 - 36 PROCESSING STATES MOTOROLA