Motorola 24-Bit Digital Signal Processor, DSP56000 manual Macr -Y0 #10, B

INSTRUCTION DESCRIPTIONS

MACR

Signed Multiply-Accumulate and Round MACR

Instruction Fields 1:
S1∗S2	Q	Q	Q	Sign	k	D	d
X0 X0	0	0	0	+	0	A	0
Y0 Y0	0	0	1	–	1	B	1
X1 X0	0	1	0
Y1 Y0	0	1	1
X0 Y1	1	0	0
Y0 X0	1	0	1
X1 Y0	1	1	0
Y1 X1	1	1	1

Note: Only the indicated S1∗S2 combinations are valid. X1∗X1 and Y1∗Y1 are not valid.

Timing: 2+mv oscillator clock cycles

Memory: 1+mv program words

Example 2:

:
MACR -Y0,		#10, B
:
			Before Execution
	Y0
		$654321

;

Y0

After Execution

$654321

B

$00:100000:000000

B

$00:0FE6AF:000000

Explanation of Example 2: The content of Y0 ($654321) is negated, multiplied by 2-10, added to the content of the B accumulator ($00:100000:000000), placed in the B accu- mulator and then rounded to a single precision number (24 bits in B1). The net effect of this operation is to negate the content of Y0, divide the result by 210 and add the result to the accumulator. An alternate interpretation is that Y0 is negated, right shifted 10 places, filled with the sign bit (0 for a positive number and 1 for a negative number), the result is added to the accumulator and then rounded to a single precision number.

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