Motorola 24-Bit Digital Signal Processor, DSP56000 manual Stop Processing State

STOP PROCESSING STATE

the first instruction fetch). If the IRQA signal is released (pulled high) after a minimum of 4T but less than 128K T cycles, no IRQA interrupt will occur, and the instruction fetched after stop cycle 8 will be the next sequential instruction (n4 in Figure 7-18). An IRQA interrupt will be serviced as shown in Figure 7-18if 1) the IRQA signal had previously been initialized as level sensitive, 2) IRQA is held low from the end of the 128K T cycle delay counter to the end of stop cycle count 8, and 3) no interrupt with a higher interrupt level is pending. If IRQA is not asserted during the last part of the STOP instruction sequence (6, 7, and 8) and if no interrupts are pending, the processor will refetch the next sequential instruction (n4). Since the IRQA signal is asserted (see Figure 7-18),the processor will recognize the interrupt and fetch and execute the instructions at P:$0008 and P:$0009 (the IRQA interrupt vector locations).

To ensure servicing IRQA immediately after leaving the stop state, the following steps must be taken before the execution of the STOP instruction:

1.Define IRQA as level sensitive – an edge-triggered interrupt will not be ser- viced.

2.Define IRQA priority as higher than the other sources and higher than the pro- gram priority.

3.Ensure that no stack error or trace interrupts are pending.

4.Execute the STOP instruction and enter the stop state.

5.Recover from the stop state by asserting the IRQA pin and holding it asserted for the whole clock recovery time. If it is low, the IRQA vector will be fetched. Also, the user must ensure that NMI will not be asserted during these last three cycles; otherwise, NMI will be serviced before IRQA because NMI prior- ity is higher.

6.The exact elapsed time for clock recovery is unpredictable. The external device that asserts IRQA must wait for some positive feedback, such as spe- cific memory access or a change in some predetermined I/O pin, before deas- serting IRQA.

The STOP sequence totals 131,104 T cycles (if SD=0) or 48 T cycles (if SD=1) in addi- tion to the period with no clocks from the stop fetch to the IRQA vector fetch (or next instruction). However, there is an additional delay if the internal oscillator is used. An indeterminate period of time is needed for the oscillator to begin oscillating and then sta- bilize its amplitude. The processor will still count 131,072 T cycles (or 16 T cycles), but

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