Motorola DSP56000, 24-Bit Digital Signal Processor manual Register and Y Memory Data Move

INSTRUCTION DESCRIPTIONS

R:Y Register and Y Memory Data Move R:Y

If the opcode-operand portion of the instruction specifies a given source or destination register, that same register or portion of that register may be used as a source S1 and/or S2 in the parallel data bus move operation. This allows data to be moved in the same instruction in which it is being used as a source operand by a data ALU operation. That is, duplicate sources are allowed within the same instruction. Note that S1 and S2 may specify the same register.

Class I Example:

:

ADDL B,A B,X1 Y:(R6)–N6,B ;2∗A+B ➞ A, update X1,B and R6

:

B

Before Execution

$80:123456:789ABC

B

After Execution

$00:654321:000000

X1

$000000

X1

$800000

R6

$2020

R6

$2000

N6

$0020

N6

$0020

Y:$2020

$654321

Y:$2020

$654321

Explanation of the Class I Example: Prior to execution, the 56-bit B accumulator con- tains the value $80:123456:789ABC, the 24-bit X1 register contains the value $000000, the 16-bit R6 address register contains the value $2020, the 16-bit N6 address offset register contains the value $0020 and the 24-bit Y memory location Y:$2020 contains the value $654321. The execution of the parallel move portion of the instruction, B,X1 Y:(R6)–N6,B, moves the 24-bit limited negative saturation constant $800000 into the X1 register since the signed integer portion of the B accumulator was in use, uses the value in the 16-bit R6 address register to move the 24-bit value in the Y memory location Y:$2020 into the 56-bit B accumulator with automatic sign extension of the upper portion of the accumulator (B2) and automatic zeroing of the lower portion of the accumulator (B0), and finally uses the contents of the 16-bit N6 address offset register to update the value in the 16-bit R6 address register. The contents of the N6 address offset register are not affected.

MOTOROLA INSTRUCTION SET DETAILS A - 193