Motorola DSP56000, 24-Bit Digital Signal Processor manual Btst #n,D

INSTRUCTION DESCRIPTIONS

BTST Bit Test

Instruction Format:

BTST #n,D

Opcode:

BTST

2316 158 70

0 0 0 0 1 0 1 1 1 1 D D D D D D 0 1 1 b b b b b

Instruction Fields:

#n=bit number=bbbbb, D=destination register=DDDDDD,

xxxx=16-bit Absolute Address in extension word

Destination Register	D D D D D D					Bit Number bbbbb
4 registers in Data ALU	0	0	0	1 D	D	00000
8 accumulators in Data ALU	0	0	1	D D	D	•
8 address registers in AGU	0	1	0	T T	T	10111
8 address offset registers in AGU	0	1	1	N N	N
8 address modifier registers in AGU	1	0	0	F F	F
8 program controller registers	1	1	1	G G	G

See Section A.10 and Table A-18for specific register encodings.

Notes: If A or B is specified as the destination operand, the following sequence of events takes place:

1.The S bit is computed according to its definition (See Section A.5)

2.The accumulator value is scaled according to the scaling mode bits S0 and S1 in the status register (SR).

3.If the accumulator extension is in use, the output of the shifter is limited to the maximum positive or negative saturation constant, and the L bit is set.

4.The bit test is performed on the resulting 24-bit value and the C bit is set if the bit tested is set. The original contents of A or B are not changed.

Timing: 4+mvb oscillator clock cycles

Memory: 1+ea program words

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