Motorola 24-Bit Digital Signal Processor, DSP56000 manual Status Register Interrupt Mask Bits

EXCEPTION PROCESSING STATE (INTERRUPT PROCESSING)

Table 7-2 Status Register Interrupt Mask Bits

I1

I0

Exceptions Permitted

Exceptions Masked

0

0

IPL 0, 1, 2, 3

None

0

1

IPL 1, 2, 3

IPL 0

1

0

IPL 2, 3

IPL 0, 1

1

1

IPL 3

IPL 0, 1, 2

ority levels, see the individual DSP56K family member’s User’s Manual.

7.3.2.1 Interrupt Priority Levels

The IPL for each on-chip peripheral device (HI, SSI, SCI) and for each external interrupt source (IRQA, IRQB) can be programmed to one of the three maskable priority levels (IPL 0, 1, or 2) under software control. IPLs are set by writing to the interrupt priority reg- ister shown in Figure 7-2.This read/write register is located in program memory at address $FFFF. It specifies the IPL for each of the interrupting devices including IRQA, IRQB and each peripheral device. (For specific peripheral information, see the specific DSP56K family member’s User’s Manual.) In addition, it specifies the trigger mode of the external interrupt sources and is used to enable or disable the individual external inter- rupts. The interrupt priority register is cleared on RESET or by the reset instruction. Table 7-3defines the IPL bits. Table 7-4defines the external interrupt trigger mode bits.

7.3.2.2 Exception Priorities Within an IPL

If more than one interrupt is pending when an instruction is executed, the processor will service the interrupt with the highest priority level first. When multiple interrupt requests

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**

10	9	8	7	6	5	4	3	2	1	0
**	*	*	*	*	IBL2	IBL1	IBL0	IAL2	IAL1	IAL0

IRQA MODE

IRQB MODE

RESERVED FOR EXPANSION

RESERVED FOR PERIPHERAL IPL LEVELS

Bits 6 to 9 are reserved, read as zero and should be written with zero for future compatibility.

Figure 7-2 Interrupt Priority Register (Addr X:$FFFF)

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