Motorola 24-Bit Digital Signal Processor, DSP56000 - page 186

PLL COMPONENTS
MOTOROLA PLL CLOCK OSCILLATOR 9 - 7
shows the programming of the DF0-DF3 bits. Changing the value of the DF0-DF3 bits
will not cause a loss of lock condition. Whenever possible, changes of the operating fre-
quency of the chip (for example, to enter a low power mode) should be made by chang-
ing the value of the DF0-DF3 bits rather than changing the MF0-MF11 bits. For MF
≤
4,
changing DF0-DF3 may lengthen the instruction cycle following the PLL control register
update; this is done in order to keep synchronization between EXTAL and the internal
chip clock. For MF>4 such synchronization is not guaranteed and the instruction cycle is
not lengthened. Note that CKOUT is synchronized with the internal clock in all cases.
The DF bits are cleared (division by one) by hardware reset.
Table 9-2 Division Factor Bits DF0-DF3
9.2.5.3 PCTL XTAL Disable Bit (XTLD) - Bit 16
The XTAL Disable (XTLD) bit controls the on-chip crystal oscillator XTAL output. When
XTLD is cleared, the XTAL output pin is active permitting normal operation of the crystal
oscillator. When XTLD is set, the XTAL output pin is held in the high (“1”) state, disabling
the on-chip crystal oscillator. If the on-chip crystal oscillator is not used (EXTAL is driven
from an external clock source), it is recommended that XTLD be set (disabling XTAL) to
minimize RFI noise and power dissipation. The XTLD bit is cleared by hardware reset.
9.2.5.4 PCTL STOP Processing State Bit (PSTP) - Bit 17
The PSTP bit controls the behavior of the PLL and of the on-chip crystal oscillator during
the STOP processing state. When PSTP is set, the PLL and the on-chip crystal oscillator
will remain operating while the chip is in the STOP processing state, enabling rapid
recovery from the STOP state. When PSTP is cleared, the PLL and the on-chip crystal
oscillator will be disabled when the chip enters the STOP processing. For minimal power
consumption during the STOP state, at the cost of longer recovery time, PSTP should be
DF3-DF0 Division
Factor DF
$0 2
0
$1 2
1
$2 2
2
••
••
$E 2
14
$F 2
15