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Motorola 24-Bit Digital Signal Processor, DSP56000 RESET PROCESSING STATE, Figure 7-13 Interrupting an REP Instruction, 7 - 34 PROCESSING STATES MOTOROLA

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RESET PROCESSING STATE7 - 34 PROCESSING STATES MOTOROLA

MAIN

PROGRAM

FETCHES

n1 REP m

INTERRUPT SYNCHRO-

NIZED AND RECOGNIZED

AS PENDING

ADDITIONAL INTERRUPTS

DISABLED DURING

FAST INTERRUPT

SERVICE ROUTINE FETCHES

(FROM BETWEEN P:$0000

AND P:$003F)

INTERRUPTS

RE-ENABLED

n2 n2

INSTRUCTION n2

REPLACED PER

THE REP INSTRUCTION

i = INTERRUPT INSTRUCTION

n = NORMAL INSTRUCTION

Figure 7-13 Interrupting an REP Instruction

(a) Instruction Fetches from Memory

INTERRUPT CONTROL CYCLE 1 ii

INTERRUPT CONTROL CYCLE 2 i% i

FETCH REP n2 n3 n4 ii1 ii2 n5 n6

DECODE REP NOP n2 n2 n2 n2 n3 n4 ii1 ii2 n5

EXECUTE REP NOP n2 n2 n2 n2 n3 n4 ii1 ii2

INSTRUCTION CYCLE COUNT 1 2 3 4 5 6 7 8 9 10 11 12

i = INTERRUPT

ii = INTERRUPT INSTRUCTION WORD

n = NORMAL INSTRUCTION WORD

i% = INTERRUPT REJECTED

INTERRUPT SYNCHRONIZED AND

RECOGNIZED AS PENDING

INTERRUPTS RE-ENABLED

(b) Program Controller Pipeline

REPEAT

m TIMES

Contents

Main Page MOTOROLA TECHNICAL DATA SEMICONDUCTOR Addendum to 24-bit Digital Signal Processor Family Manual DSP56K Family Page Page TABLE OF CONTENTS Page Page Page LIST of FIGURES Page List of Figures (Continued) LIST of TABLES Table Page List of Tables (Continued) Table Page Page Page Page Page Page Page Page Page Page MAC Page Page Page Page Page Page ADDRESS BUSES 2- 4 DSP56K CENTRAL ARCHITECTURE OVERVIEW Figure 2-1 DSP56K Block Diagram 2.3 ADDRESS BUSES Page Page Page Page Page OVERVIEW AND DATA ALU ARCHITECTURE 3 - 4 DATA ARITHMETIC LOGIC UNIT Figure 3-1 DSP56K Block Diagram 24 Bit 56K Page Page + Page Page Page Page Page Page Page DATA REPRESENTATION AND ROUNDING Figure 3-10 Convergent Rounding DATA ARITHMETIC LOGIC UNIT 3 - 15 CAUTION: Page Page Page Page Page Page Page AGU ARCHITECTURE 4 - 4 ADDRESS GENERATION UNIT Figure 4-1 DSP56K Block Diagram 4.2.2 Offset Register Files (Nn) Page Page Page Page Page Page Page Page Page Page Page Page ADDRESSING Table 4-2 Address Modifier Summary 4 - 18 ADDRESS GENERATION UNIT MOTOROLA Page Page Page Page Page Page Page ADDRESSING Figure 4-15 Address Modifier Summary 4 - 26 ADDRESS GENERATION UNIT MOTOROLA Page Page Page OVERVIEW 5 - 4 PROGRAM CONTROL UNIT Figure 5-2 DSP56K Block Diagram 24-Bit 56K Mod- Page Page PROGRAM CONTROL UNIT (PCU) ARCHITECTURE Figure 5-3 Three-Stage Pipeline PROGRAM CONTROL UNIT 5 - 7 Page Page Page Page Page Page * Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page INSTRUCTION FORMATS Figure 6-7 Special Addressing Immediate Data 6 - 16 INSTRUCTION SET INTRODUCTION MOTOROLA when used to address program memory. This addressing mode is classified as a program reference. Page INSTRUCTION FORMATS 6 - 18 INSTRUCTION SET INTRODUCTION MOTOROLA Arithmetic Bit Manipulation Move INSTRUCTION GROUPS 6 - 20 INSTRUCTION SET INTRODUCTION MOTOROLA Figure 6-11 Special Addressing Absolute Short Address Page INSTRUCTION GROUPS 6 - 22 INSTRUCTION SET INTRODUCTION MOTOROLA Table 6-1 Addressing Modes Summary Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page CAUTION Figure 7-1 Fast and Long Interrupt Examples RECOGNIZED (b) DSP56K Long Interrupt and their IPLs are listed in Table 7-6. For information on on-chip peripheral interrupt pri- PROCESSING STATES 7 - 13 (a) DSP56K Fast Interrupt FAST INTERRUPT SERVICE ROUTINE LONG INTERRUPT SERVICE ROUTINE Page Page Page Page CAUTION Page 7 - 20 PROCESSING STATES MOTOROLA Figure 7-5 Illegal Instruction Interrupt Serviced by a Long Interrupt Page Page MOTOROLA PROCESSING STATES 7 - 23 Figure 7-7 Trace Exception Page Page Page MOTOROLA PROCESSING STATES 7 - 27 Figure 7-8 Fast Interrupt Service Routine 7 - 28 PROCESSING STATES MOTOROLA i = INTERRUPT ii = INTERRUPT INSTRUCTION WORD n = NORMAL INSTRUCTION WORD Figure 7-9 Two Consecutive Fast Interrupts Page 7 - 30 PROCESSING STATES MOTOROLA Figure 7-10 Long Interrupt Service Routine MOTOROLA PROCESSING STATES 7 - 31 Figure 7-11 JSR First Instruction of a Fast Interrupt 7 - 32 PROCESSING STATES MOTOROLA Figure 7-12 JSR Second Instruction of a Fast Interrupt Page RESET PROCESSING STATE Figure 7-13 Interrupting an REP Instruction 7 - 34 PROCESSING STATES MOTOROLA RESET PROCESSING STATE MOTOROLA PROCESSING STATES 7 - 35 i = INTERRUPT ii = INTERRUPT INSTRUCTION WORD n = NORMAL INSTRUCTION WORD i% = INTERRUPT REJECTED Figure 7-14 Interrupting Sequential REP Instructions Page Page Page Page Page Page Page Page Page Page Page Page PORT A INTERFACE 8 - 4 PORT A Figure 8-1 Port A Signals signals (A0-A15), data bus signals (D0-D15), and bus control. The bus control signals can Page Page Page Page Page Page Page PLL COMPONENTS 9 - 4 PLL CLOCK OSCILLATOR Figure 9-2 DSP56K Block Diagram 9.2.1 Phase Detector and Charge Pump Loop Filter Page 01267891011 345 121314181920212223 151617 Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page .. Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page SECTION 11 ADDITIONAL SUPPORT Dr. BuB Electronic Bulletin Board ola Motorola DSP Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page SECTION 12 Dr. BuB Electronic Bulletin Board ola Motorola DSP Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page INSTRUCTION SET DETAILS A - 1 APPENDIX A INSTRUCTION SET DETAILS Bit Field Manipulation Loop Move Page Page Page Page Page Page Page Page Page Page ADDRESSING MODES A - 12 INSTRUCTION SET DETAILS Table A-3 DSP56K Addressing Mode Encoding Page ADDRESSING MODES A - 14 INSTRUCTION SET DETAILS Table A-4 Addressing Mode Modifier Summary Page Page Page Page CONDITION CODE COMPUTATION The following notes apply to Table A-5: MOTOROLA INSTRUCTION SET DETAILS A - 19 Table A-5 Condition Code Computations for Instructions (No Parallel Move) Page Page Page ABS Page ADC Page ADD Add ADD Page ADDL Page ADDR Page AND Page ANDI Page ASL Page ASR Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page BTST Page Page Page CLR Page CMP Compare CMP Page CMPM DEBUG Page Page DEBUGcc Page DEC Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page ENDDO Page EOR Page ILLEGAL Page INC Page Page Page Page Page Page Page Page Page Page Page JMP Jump JMP Page + Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page JSR Page Page Page Page Page Page Page LSL Page LSR Page LUA Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page U Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page (S1 2-n)D (no parallel move) MPY ( Page Page Page Page Page Page Page Page NEG Page NOP Page NORM Page NOT Page OR Page ORI Page Page Page Page Page Page Page Page Page RESET Page Page Page Page Page ROL Page ROR Page RTI Page RTS Page Page Page Page Page STOP Page SUB Subtract SUB Page SUBL Page SUBR Page SWI Page Page Page Page Page TFR Page TST Page WAIT Page Page Page B - 4 BENCHMARK PROGRAMS Table B-1 27-MHz Benchmark Results for the DSP56001R27 Page B - 6 BENCHMARK PROGRAMS Figure B-1 20-Tap FIR Filter Example (Sheet 1 of 2) Page B - 8 BENCHMARK PROGRAMS Figure B-1 20-Tap FIR Filter Example (Sheet 2 of 2) Page B - 10 BENCHMARK PROGRAMS Figure B-2 Radix 2, In-Place, Decimation-In-Time FFT (Sheet 1 of 2) Page B - 12 BENCHMARK PROGRAMS Figure B-5 Real Input FFT Based on Glenn Bergland Algorithm (Sheet 1 of 8) Figure B-2 Radix 2, In-Place, Decimation-In-Time FFT (Sheet 2 of 2) Page B - 14 BENCHMARK PROGRAMS Figure B-5 Real Input FFT Based on Glenn Bergland Algorithm (Sheet 3 of 8) Figure B 3 8 Pole 4 Multiply Cascaded Canonic IIR Filter (Sheet 1 of 2) Page B - 16 BENCHMARK PROGRAMS Figure B-5 Real Input FFT Based on Glenn Bergland Algorithm (Sheet 5 of 8) Page B - 18 BENCHMARK PROGRAMS Figure B-5 Real Input FFT Based on Glenn Bergland Algorithm (Sheet 7 of 8) Figure B-5 Real Input FFT Based on Glenn Bergland Algorithm (Sheet 8 of 8) BENCHMARK PROGRAMS B - 19 B - 20 BENCHMARK PROGRAMS BENCHMARK PROGRAMS B - 21 B - 22 BENCHMARK PROGRAMS BENCHMARK PROGRAMS B - 23 B - 24 BENCHMARK PROGRAMS BENCHMARK PROGRAMS B - 25 Page Page Page INDEX C B A INDEX - 2 G F E D L J I H INDEX - 4 P N M O R INDEX - 5