Motorola DSP56000, 24-Bit Digital Signal Processor manual Port a Overview, Port a Interface

PORT A OVERVIEW

8.1PORT A OVERVIEW

Port A provides a versatile interface to external memory, allowing economical connection with fast memories, slow memories/devices, and multiple bus master systems. This sec- tion introduces the signals associated with this memory expansion port that are common among the members of the DSP56K family of processors which feature Port A. Certain characteristics, such as signaling, timing, and bus arbitration, vary between members of the processor family and are detailed in each device’s own User’s Manual.

Port A has two power-reduction features. It can access internal memory spaces, toggling only the external memory signals that need to change, and eliminate unneeded switch- ing current. Also, if conditions allow the processor to operate at a lower memory speed, wait states can be added to the external memory access to significantly reduce power while the processor accesses those memories.

8.2PORT A INTERFACE

The DSP56K processor can access one or more of its memory sources (X data memory, Y data memory, and program memory) while it executes an instruction. The memory sources may be either internal or external to the DSP. Three address buses (XAB, YAB, and PAB) and four data buses (XDB, YDB, PDB, and GDB) are available for internal memory accesses during one instruction cycle. Port A’s one address bus and one data bus are available for external memory accesses. If all memory sources are internal to the DSP, one or more of the three memory sources may be accessed in one instruction cycle (i.e., program memory access or program memory access plus an X, Y, XY, or L memory reference). However, when one or more of the memories are external to the chip, memory references may require additional instruction cycles because only one external memory access can occur per instruction cycle.

If an instruction cycle requires more than one external access, the processor will make the accesses in the following priority: X memory, Y memory, and program memory. It takes one instruction cycle for each external memory access – i.e., one access can be executed in one instruction cycle, two accesses take two instruction cycles, etc. Since the external bus is only 24 bits wide, one XY or long external access will take two instruction cycles.

The port A external data bus shown in Figure 8-1is 24 bits wide. The 16-bit address bus can sustain a rate of one memory access per instruction cycle (using no-wait-state mem- ory which is discussed in Section 8.2.5.)

Figure 8-1shows the port A signals divided into their three functional groups: address bus

MOTOROLA PORT A 8 - 3