SUMMARY OF DSP56K FAMILY FEATURES

architecture matches the shape of the MAC operation. The two operands, C() and X(), are directed to a multiply operation, and the result is summed. This process is built into the chip by using two separate memories (X and Y) to feed a single-cycle MAC. The entire process must occur under program control to direct the correct operands to the multiplier and save the accumulator as needed. Since the two memories and the MAC are indepen- dent, the DSP can perform two moves, a multiply and an accumulate, in a single operation. As a result, many of the benchmarks shown in Table 1-1 can be executed at or near the theoretical maximum speed for a single-multiplier architecture.

1.3SUMMARY OF DSP56K FAMILY FEATURES

The high throughput of the DSP56K family of processors makes them well suited for com- munication, high-speed control, numeric processing and computer and audio applications. The main features that contribute to this high throughput include:

Speed — Speeds high enough to easily address applications traditionally served by low-end floating point DSPs.

x(t)

A/D

x(n)

FIR FILTER

N

c(k ) ⋅ (n k )

k = 0

D/A

y(n)

y(t)

X

X

MEMORY

X

Y

MEMORY

PROGRAM

MAC

Figure 1-3 DSP Hardware Origins

MOTOROLA

DSP56K FAMILY INTRODUCTION

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Motorola DSP56000, 24-Bit Digital Signal Processor manual Summary of DSP56K Family Features, DSP Hardware Origins