Motorola 24-Bit Digital Signal Processor, DSP56000 manual Set if overflow bit V is set

Set if the MS bit of the destination operand is changed as a result of the instruction’s left shift operation

Set if bit 55 of the result is cleared.

INSTRUCTION DESCRIPTIONS

DIV

Divide Interation

DIV

A complete discussion of the various division routines is beyond the scope of this man- ual. For a more complete discussion of these routines, refer to the application note enti- tled Fractional and Integer Arithmetic Using the DSP56001.

For extended precision division (i.e., for N-bit quotients where N>24), the DIV instruction is no longer applicable, and a user-defined N-bit division routine is required. For further information on division algorithms, refer to pages 524–530 of Theory and Application of Digital Signal Processing by Rabiner and Gold (Prentice-Hall, 1975), pages 190–199 of Computer Architecture and Organization by John Hayes (McGraw-Hill, 1978), pages 213–223 of Computer Arithmetic: Principles, Architecture, and Design by Kai Hwang (John Wiley and Sons, 1979), or other references as required.

Condition Codes:

15	14	13	12	11		10	9		8	7	6	5	4	3	2	1		0
LF	DM	T	**		S1	S0		I1	I0	S	L	E	U	N	Z		V	C
				MR									CCR

L — Set if overflow bit V is set

V —

C —

A - 86 INSTRUCTION SET DETAILS MOTOROLA