INSTRUCTION DESCRIPTIONS
A - 40 INSTRUCTION SET DETAILS MOTOROLA
Operation: Assembler Syntax:
D[n] ➞ C; BCHG #n,X:ea
D[n] ➞ D[n]
D[n] ➞ C; BCHG #n,X:aa
D[n] ➞ D[n]
D[n] ➞ C; BCHG #n,X:pp
D[n] ➞ D[n]
D[n] ➞ C; BCHG #n,Y:ea
D[n] ➞ D[n]
D[n] ➞ C; BCHG #n,Y:aa
D[n] ➞ D[n]
D[n] ➞ C; BCHG #n,Y:pp
D[n] ➞ D[n]
D[n] ➞ C; BCHG #n,D
D[n] ➞ D[n]
Description: Test the nth bit of the destination operand D, complement it, and store the
result in the destination location. The state of the nth bit is stored in the carry bit C of the
condition code register. The bit to be tested is selected by an immediate bit number from
0–23. This instruction performs a read-modify-write operation on the destination location
using two destination accesses before releasing the bus. This instruction provides a test-
and-change capability which is useful for synchronizing multiple processors using a
shared memory. This instruction can use all memory alterable addressing modes.
Example: :
BCHG #$7,X:<<$FFE2 ;test and change bit 7 in I/O Port B DDR
:
BCHG Bit Test and Change BCHG
Before Execution After Execution
X:$FFE2 X;$FFE2
$000000
SR SR
$0300 $0300
$000080