Motorola DSP56000, 24-Bit Digital Signal Processor manual Data Buses

DSP56K CENTRAL ARCHITECTURE OVERVIEW

2.1DSP56K CENTRAL ARCHITECTURE OVERVIEW

The DSP56K family of processors is built on a standard central processing module. In the expansion area around the central processing module, the chip can support various con- figurations of memory and peripheral modules which may change from family member to family member. This section introduces the architecture and the major components of the central processing module.

The central components are:

•Data Buses

•Address Buses

•Data Arithmetic Logic Unit (data ALU)

•Address Generation Unit (AGU)

•Program Control Unit (PCU)

•Memory Expansion (Port A)

•On-Chip Emulator (OnCE™) circuitry

•Phase-locked Loop (PLL) based clock circuitry

Figure 2-1shows a block diagram of a typical DSP56K family processor, including the central processing module and a nonspecific expansion area for memory and peripherals. The following paragraphs give brief descriptions of each of the central components. Each of the components is explained in detail in subsequent chapters.

2.2DATA BUSES

The DSP56K central processing module is organized around the registers of three inde- pendent execution units: the PCU, the AGU, and the data ALU. Data movement between the execution units occurs over four bidirectional 24-bit buses: the X data bus (XDB), the Y data bus (YDB), the program data bus (PDB), and the global data bus (GDB). (Certain instructions treat the X and Y data buses as one 48-bit data bus by concatenating them.) Data transfers between the data ALU and the X data memory or Y data memory occur over XDB and YDB, respectively. XDB and YDB are kept local on the chip to maximize speed and minimize power dissipation. All other data transfers, such as I/O transfers with peripherals, occur over the GDB. Instruction word prefetches occur in parallel over the PDB.

The bus structure supports general register-to-register, register-to-memory, and memory- to-register data movement. It can transfer up to two 24-bit words and one 56-bit word in the same instruction cycle. Transfers between buses occur in the internal bus switch.

MOTOROLA DSP56K CENTRAL ARCHITECTURE OVERVIEW 2 - 3