Ordering Information, Package Diagram | Cypress CY7C67200 specification

					CY7C67200
					CY7C67200



Ordering Information
Table 43.Ordering Information

Ordering Code			Package Type	PB-Free	Temperature Range
CY7C67200-48BAXI			48FBGA	X	–40 to 85°C

CY7C67200-BAXIT			48FBGA, Tape and reel	X	–40 to 85°C

CY3663			Development Kit

Package Diagram

48-Ball (7.00 mm x 7.00 mm x 1.2 mm) FBGA BA48

7.00±0.10

A

B

0.25 C

0.53±0.05

0.36

TOP VIEW

PIN 1 CORNER (LASER MARK)

1 2 3 4 5 6

A

B

C

D

E

F

G

H

7.00±0.10

0.21±0.05

0.10 C

SEATING PLANE

C

1.20 MAX.

7.00±0.10	5.25	0.75	2.625
A

B

0.15(4X)

BOTTOM VIEW

PIN 1 CORNER

Ø0.05 M C

Ø0.25 M C A B

Ø0.30±0.05(48X)

6 5 4 3 2 1

A

B

C

D

E

F

G

H

1.875

0.75

3.75 7.00±0.10

51-85096-*F

Purchase of I2C™ components from Cypress, or one of its sublicensed Associated Companies, conveys a license under the Philips I2C Patent Rights to use these components in an I2C system, provided that the system conforms to the I2C Standard Specification as defined by Philips. EZ-OTG is a trademark of Cypress Semiconductor. All product and company names mentioned in this document are trademarks of their respective holders.

Document #: 38-08014 Rev. *G

Page 77 of 78

© Cypress Semiconductor Corporation, 2006. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.

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Image 77

Cypress CY7C67200 manual Package Diagram, Ordering Information Ordering Code Package Type PB-Free

Contents

Typical Applications EZ-OTG FeaturesCY7C67200 CY16 Interface Descriptions IntroductionProcessor Core Functional Overview OTG Interface Pins Pin Name Pin Number USB Interface Pins Pin Name Pin NumberUSB Interface OTG Interface SPI Interface Pins Pin Name Pin Number I2C Eeprom Interface Pins Pin Name Pin NumberHSS Interface Pins Pin Name Pin Number Serial Peripheral Interface Host Port Interface HPI HPI Interface Pins 1 Pin Name Pin NumberHPI Addressing HPI A10 Charge Pump Interface Crystal Interface Charge Pump Interface Pins Pin Name Pin NumberBooster Interface Boot Configuration Interface Crystal Pins Pin Name Pin NumberBoot Mode Pin Sleep Power Savings and Reset DescriptionPower Savings Mode Description Memory Map Registers Bank Register Example Hex Value Binary Value Bank Register 0xC002 R/WReserved Hardware Revision Register 0xC004 R CPU Speed Definition Processor Speed CPU Speed Register 0xC008 R/W Host/Device 1 Wake Enable Bit Host/Device 2 Wake Enable BitOTG Wake Enable Bit HSS Wake Enable Bit OTG Interrupt Enable Bit Halt Enable BitSPI Interrupt Enable Bit Host/Device 2 Interrupt Enable Bit Gpio Interrupt Enable Bit Uart Interrupt Enable BitTimer 1 Interrupt Enable Bit Timer 0 Interrupt Enable Bit Port 1A Diagnostic Enable Bit Port 2A Diagnostic Enable BitPull-down Enable Bit LS Pull-up Enable Bit Lock Enable Bit Timeout Flag BitWDT Enable Bit Reset Strobe Bit General USB Registers Timer n Register R/WUSB Registers Register Name Address SIE1/SIE2 0xC08A/0xC0AA Port a Resistors Enable Bit Mode Select BitUSB Data Line Pull-up and Pull-down Resistors Mode Port n Resistors Function Select Enable Sync Enable Bit Preamble Enable BitISO Enable Bit Arm Enable Bit Host 1 Count Register 0xC084 Host 2 Count Register 0xC0A4 Host n Address Register R/WHost n Count Register R/W Underflow Flag Bit Error Flag BitStall Flag Bit NAK Flag Bit Host n PID Register W ACK Flag BitPID Select Definition PID Select Host n Device Address Register W Host n Count Result Register R ID Interrupt Enable Bit Vbus Interrupt Enable BitSOF/EOP Interrupt Enable Bit Port a Wake Interrupt Enable Bit ID Interrupt Flag Bit Vbus Interrupt Flag BitSOF/EOP Interrupt Flag Bit Port a Wake Interrupt Flag Bit Host n SOF/EOP Counter Register R Host n SOF/EOP Count Register R/WCount Bits Count field sets the SOF/EOP counter duration USB Device Only Registers Reserved Host n Frame Register RUSB Device Only Registers Register Name Address Device 1/Device Stall Enable Bit IN/OUT Ignore Enable BitNAK Interrupt Enable Bit Enable Bit Device n Endpoint n Count Register R/W Device n Endpoint n Address Register R/W OUT Exception Flag Bit Device n Endpoint n Status Register R/W Timeout occurred Timeout condition did not occur Setup Flag BitError occurred Error did not occur Exception Flag Bit Device n Endpoint n Count Result Register Device n Endpoint n Count Result Register R/W SOF/EOP Timeout Interrupt Enable Bit Device n Interrupt Enable Register R/WReset Interrupt Enable Bit EP7 Interrupt Enable Bit EP4 Interrupt Enable Bit EP5 Interrupt Enable Bit EP2 Interrupt Enable BitEP3 Interrupt Enable Bit EP1 Interrupt Enable Bit Device n Status Register R/W Device n Address Register W EP7 Interrupt Flag Bit Reset Interrupt Flag BitEP6 Interrupt Flag Bit EP5 Interrupt Flag Bit SOF/EOP Timeout Interrupt Counter Bits SOF/EOP Timeout Flag BitDevice n Frame Number Register R Device n SOF/EOP Count Register W Receive Disable Bit Vbus Pull-up Enable BitCharge Pump Enable Bit Vbus Discharge Enable Bit SAS Enable Bit Write Protect Enable BitMode Select Definition Gpio Configuration 108 111 Reserved Vbus Valid Flag Bit SPI Enable Bit HSS Enable BitInterrupt 0 Enable Bit Interrupt 0 Polarity Select Bit Gpio 0 Direction Register 0xC022 R/W Gpio 0 Input Data Register 0xC020 RGpio 1 Input Data Register 0xC026 R HSS Registers Register Name Address Gpio 1 Direction Register 0xC028 R/WHSS Registers CTS Enable Bit Xoff Enable BitReceive Interrupt Enable Bit RTS Polarity Select Bit Transmit Ready Bit Packet Mode Select BitReceive Overflow Flag Bit Receive Packet Ready Flag Bit HSS Data Register 0xC076 R/W HSS Transmit Gap Register 0xC074 R/WTransmit Gap Select Bits HSS Receive Counter Register 0xC07A R/W HSS Receive Address Register 0xC078 R/W HSS Transmit Counter Register 0xC07E R/W HSS Transmit Address Register 0xC07C R/WHPI Registers HPI Registers Register Name Address ID to HPI Enable Bit Vbus to HPI Enable BitSOF/EOP2 to HPI Enable Bit HPI Breakpoint Register 0x0140 R SOF/EOP1 to HPI Enable Bit SOF/EOP2 to CPU Enable BitSOF/EOP1 to CPU Enable Bit Reset2 to HPI Enable Bit SIE1msg Register SIE2msg Register SIEXmsg Register WData Bits HPI Mailbox Register 0xC0C6 R/W Vbus Flag Bit Reset2 Flag BitID Flag Bit SOF/EOP2 Flag Bit Done1 Flag Bit SPI Registers Reset1 Flag BitMailbox Out Flag Bit SPI Registers Register Name Address Phase Select Bit 3Wire Enable BitMaster Active Enable Bit Master Enable Bit Read Enable Bit Byte Mode BitSCK Strobe Bit Fifo Init Bit Transfer Interrupt Enable Bit Transmit Interrupt Enable BitFifo Error Flag Bit Receive Bit Length Bits Transmit Interrupt Flag Bit CRC Mode Definition CRCMode CRC PolynomialTransfer Interrupt Flag Bit Transmit Interrupt Clear Bit CRC Clear Bit CRC Enable BitReceive CRC Bit One in CRC Bit SPI Transmit Count Register 0xC0DA R/W SPI Transmit Address Register 0xC0D8 R/W SPI Receive Count Register 0xC0DE R/W SPI Receive Address Register 0xC0DC R/WUart Registers Uart Registers Register Name Address Scale Select Bit Uart Enable BitBaud Select Bits Uart Baud Select Definition Baud Rate DIV8 = Uart Data Register 0xC0E4 R/W Transmit Full Bit Pin Descriptions Name Type Pin DiagramPin Descriptions A1 HPI A1 GPIO20 General Purpose IOGPIO19 General Purpose IO A0 HPI A0 Absolute Maximum Ratings Booster Power Input 2.7V toOperating Conditions Crystal Requirements XTALIN, Xtalout DC Characteristics Reset Timing AC Timing Characteristics Parameter Description Min Typical Max Unit Clock TimingI2C Eeprom Timing HPI Host Port Interface Write Cycle Timing HPI Host Port Interface Read Cycle Timing Data Access Time, from HPInRD fallingRead Pulse Width Read Cycle Time Document # 38-08014 Rev. *G HSS Byte and Block Mode Receive HSS Byte Mode TransmitHSS Block Mode Transmit Hssrts Hsscts Hardware CTS/RTS Handshake Register Summary Register Summary GPIO31 GPIO30 GPIO29 SE0 SOF/EOP2 Ordering Information Package DiagramOrdering Information Ordering Code Package Type PB-Free Ball 7.00 mm x 7.00 mm x 1.2 mm Fbga BA48 Document History Issue Orig. Description of Change Date