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Cypress CY7C67200 manual Bank Register 0xC002 R/W, Hardware Revision Register 0xC004 R

Models: CY7C67200

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Bank Register [0xC002] [R/W]

CY7C67200

Bank Register [0xC002] [R/W]

Figure 8. Bank Register

Bit #	15	14	13	12		11	10	9	8
Field					Address...
Read/Write	R/W	R/W	R/W	R/W		R/W	R/W	R/W	R/W
Default	0	0	0	0		0	0	0	1

Bit #	7	6	5	4	3	2	1	0
Field		...Address				Reserved
Read/Write	R/W	R/W	R/W	-	-	-	-	-
Default	0	0	0	X	X	X	X	X

Register Description

The Bank register maps registers R0–R15 into RAM. The eleven MSBs of this register are used as a base address for registers R0–R15. A register address is automatically generated by:

1.Shifting the four LSBs of the register address left by 1

2.ORing the four shifted bits of the register address with the 12 MSBs of the Bank Register

3.Forcing the LSB to zero

For example, if the Bank register is left at its default value of 0x0100, and R2 is read, then the physical address 0x0102 will be read. See Table 17 for details.

.

Table 17.Bank Register Example

Register	Hex Value	Binary Value
Bank	0x0100	0000 0001 0000 0000

R14	0x000E << 1 = 0x001C	0000 0000 0001 1100

RAM	0x011C	0000 0001 0001 1100
Location

Address (Bits [15:4])

The Address field is used as a base address for all register addresses to start from.

Reserved

All reserved bits must be written as ‘0’.

Hardware Revision Register [0xC004] [R]

Figure 9. Revision Register

Bit #	15	14	13	12		11	10	9	8
Field					Revision...
Read/Write	R	R	R	R		R	R	R	R
Default	X	X	X	X		X	X	X	X

Bit #	7	6	5		4		3		2	1	0
Field						...Revision
Read/Write	R	R	R		R		R		R	R	R
Default	X	X	X		X		X		X	X	X
Register Description						Revision (Bits [15:0])
The Hardware Revision register is a read-only register that						The Revision field contains the silicon revision number.
indicates the silicon revision number. The first silicon revision

is represented by 0x0101. This number is increased by one for each new silicon revision.

Document #: 38-08014 Rev. *G

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Cypress CY7C67200 manual Bank Register 0xC002 R/W, Hardware Revision Register 0xC004 R

Contents

CY7C67200 EZ-OTG FeaturesCY7C67200 Typical ApplicationsCY7C67200 IntroductionProcessor Core Functional Overview Interface DescriptionsOTG Pins USB FeaturesUSB Pins OTG FeaturesI2C EEPROM Pins UART FeaturesUART Pins I2C EEPROM FeaturesCY7C67200 HPI FeaturesHPI Pins CY7C67200CY7C67200 Charge Pump FeaturesCharge Pump Pins Booster PinsCY7C67200 Crystal PinsCoprocessor Mode Standalone ModePower Savings Mode Description Power Savings and Reset DescriptionMinimum Hardware Requirements for Standalone Mode - Peripheral Only Figure 5. Minimum Standalone Hardware Configuration - Peripheral Only0x0000 - 0x00FF 0x0100 - 0x011F 0x0120 - 0x013F LCP Variables USB Registers Slave Setup Packet BIOS StackMemory Map Internal MemoryCY7C67200 RegistersCPU Flags Register 0xC000 R CY7C67200 Bank Register 0xC002 R/WHardware Revision Register 0xC004 R CY7C67200 CPU Speed Register 0xC008 R/WCY7C67200 Power Control Register 0xC00A R/WCY7C67200 Interrupt Enable Register 0xC00E R/WCY7C67200 Breakpoint Register 0xC014 R/WForce Select USB Diagnostic Register 0xC03C R/WCY7C67200 Pull-downStrobe Watchdog Timer Register 0xC00C R/WCY7C67200 LockCY7C67200 Timer n Register R/WUSB n Control Register R/W Resistors Enable0xC094/0xC0B4 CY7C67200Pull up/Pull down on D+ and 0xC090/0xC0B0Sync Host n Control Register R/WCY7C67200 SequenceCY7C67200 Host n Address Register R/WHost n Count Register R/W Length Host n Endpoint Status Register RCY7C67200 CY7C67200 Host n PID Register WCY7C67200 Host n Count Result Register RHost n Device Address Register W Port A Connect Host n Interrupt Enable Register R/WCY7C67200 Port A Connect Host n Status Register R/WCY7C67200 CY7C67200 Host n SOF/EOP Count Register R/WHost n SOF/EOP Counter Register R CY7C67200 Host n Frame Register RDevice n Endpoint n Control Register R/W CY7C67200 CY7C67200 Device n Endpoint n Address Register R/WDevice n Endpoint n Count Register R/W CY7C67200 Device n Endpoint n Status Register R/WSetup Page 32 of CY7C67200CY7C67200 Device n Endpoint n Count Result Register R/WCY7C67200 Device n Interrupt Enable Register R/WInterrupt Enable Page 35 of CY7C67200CY7C67200 Device n Address Register WDevice n Status Register R/W Page 37 of CY7C67200CY7C67200 Device n Frame Number Register RDevice n SOF/EOP Count Register W C098H OTG Control Register 0xC098 R/WCY7C67200 CY7C67200 GPIO Control Register 0xC006 R/WCY7C67200 GPIO 0 Output Data Register 0xC01E R/WGPIO 1 Output Data Register 0xC024 R/W CY7C67200 GPIO 0 Input Data Register 0xC020 RGPIO 1 Input Data Register 0xC026 R GPIO 0 Direction Register 0xC022 R/WCY7C67200 GPIO 1 Direction Register 0xC028 R/WCY7C67200 HSS Control Register 0xC070 R/WCY7C67200 HSS Baud Rate Register 0xC072 R/WCY7C67200 HSS Transmit Gap Register 0xC074 R/WHSS Data Register 0xC076 R/W CY7C67200 HSS Receive Address Register 0xC078 R/WHSS Receive Counter Register 0xC07A R/W CY7C67200 HSS Transmit Address Register 0xC07C R/WHSS Transmit Counter Register 0xC07E R/W CY7C67200 HPI Breakpoint Register 0x0140 RInterrupt Routing Register 0x0142 R CY7C67200 SOF/EOP2 to CPU Enable BitCY7C67200 SIEXmsg Register WHPI Mailbox Register 0xC0C6 R/W CY7C67200 HPI Status Port HPI RCY7C67200 SPI Configuration Register 0xC0C8 R/WCY7C67200 3Wire Enable BitReceive Bit Length SPI Control Register 0xC0CA R/WCY7C67200 StrobeCY7C67200 SPI Interrupt Enable Register 0xC0CC R/WSPI Status Register 0xC0CE R CY7C67200 SPI Interrupt Clear Register 0xC0D0 WSPI CRC Control Register 0xC0D2 R/W CY7C67200 SPI CRC Value Register 0xC0D4 R/WSPI Data Register 0xC0D6 R/W CY7C67200 SPI Transmit Address Register 0xC0D8 R/WSPI Transmit Count Register 0xC0DA R/W CY7C67200 SPI Receive Address Register 0xC0DC R/WSPI Receive Count Register 0xC0DE R/W CY7C67200 UART Control Register 0xC0E0 R/WUART Status Register 0xC0E2 R CY7C67200 UART Data Register 0xC0E4 R/WCY7C67200 Pin DiagramPin Descriptions Type CY7C67200Table 38.Pin Descriptions continued NameCY7C67200 Absolute Maximum RatingsOperating Conditions Crystal Requirements XTALIN, XTALOUTCY7C67200 DC CharacteristicsCY7C67200 AC Timing CharacteristicsReset Timing nRESET nRD or nWRL or nWRHCY7C67200 Clock Timing1. I2C EEPROM Bus Timing - Serial I/O XTALINtCYC ADDR nCS nWR nRD DoutCY7C67200 tASU tCSSUCY7C67200 ADDRHSS BYTE and BLOCK Mode Receive CY7C67200HSS BYTE Mode Transmit HSS Block Mode TransmitPage 72 of CY7C67200Hardware CTS/RTS Handshake CY7C67200 Register SummaryDefault High Default Low+ Feedback Default HighDefault Low CY7C67200+ Feedback Default HighDefault Low CY7C67200+ Feedback Default HighDefault Low CY7C67200Table 43.Ordering Information Package DiagramOrdering Information CY7C67200Mode” Document History Page“Interrupt Enable Register 0xC00E R/W” CY7C67200