Bank Register 0xC002 R/W, Reserved | Cypress CY7C67200 instruction

CY7C67200

Bank Register [0xC002] [R/W]

Figure 8. Bank Register

Bit #	15	14	13	12		11	10	9	8
Field					Address...
Read/Write	R/W	R/W	R/W	R/W		R/W	R/W	R/W	R/W
Default	0	0	0	0		0	0	0	1

Bit #	7	6	5	4	3	2	1	0
Field		...Address				Reserved
Read/Write	R/W	R/W	R/W	-	-	-	-	-
Default	0	0	0	X	X	X	X	X

Register Description

The Bank register maps registers R0–R15 into RAM. The eleven MSBs of this register are used as a base address for registers R0–R15. A register address is automatically generated by:

1.Shifting the four LSBs of the register address left by 1

2.ORing the four shifted bits of the register address with the 12 MSBs of the Bank Register

3.Forcing the LSB to zero

For example, if the Bank register is left at its default value of 0x0100, and R2 is read, then the physical address 0x0102 will be read. See Table 17 for details.

.

Table 17.Bank Register Example

Register	Hex Value	Binary Value
Bank	0x0100	0000 0001 0000 0000

R14	0x000E << 1 = 0x001C	0000 0000 0001 1100

RAM	0x011C	0000 0001 0001 1100
Location

Address (Bits [15:4])

The Address field is used as a base address for all register addresses to start from.

Reserved

All reserved bits must be written as ‘0’.

Hardware Revision Register [0xC004] [R]

Figure 9. Revision Register

Bit #	15	14	13	12		11	10	9	8
Field					Revision...
Read/Write	R	R	R	R		R	R	R	R
Default	X	X	X	X		X	X	X	X

Bit #	7	6	5		4		3		2	1	0
Field						...Revision
Read/Write	R	R	R		R		R		R	R	R
Default	X	X	X		X		X		X	X	X
Register Description						Revision (Bits [15:0])
The Hardware Revision register is a read-only register that						The Revision field contains the silicon revision number.
indicates the silicon revision number. The first silicon revision

is represented by 0x0101. This number is increased by one for each new silicon revision.

Document #: 38-08014 Rev. *G

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Cypress CY7C67200 manual Bank Register 0xC002 R/W, Bank Register Example Hex Value Binary Value, Reserved

Contents

CY16 EZ-OTG FeaturesTypical Applications CY7C67200 Interface Descriptions IntroductionProcessor Core Functional Overview OTG Interface USB Interface Pins Pin Name Pin NumberOTG Interface Pins Pin Name Pin Number USB Interface Serial Peripheral Interface I2C Eeprom Interface Pins Pin Name Pin NumberSPI Interface Pins Pin Name Pin Number HSS Interface Pins Pin Name Pin Number Charge Pump Interface HPI Interface Pins 1 Pin Name Pin NumberHost Port Interface HPI HPI Addressing HPI A10 Crystal Interface Charge Pump Interface Pins Pin Name Pin NumberBooster Interface Pin Crystal Pins Pin Name Pin NumberBoot Configuration Interface Boot Mode Sleep Power Savings and Reset DescriptionPower Savings Mode Description Memory Map Registers Hardware Revision Register 0xC004 R Bank Register 0xC002 R/WBank Register Example Hex Value Binary Value Reserved CPU Speed Definition Processor Speed CPU Speed Register 0xC008 R/W HSS Wake Enable Bit Host/Device 2 Wake Enable BitHost/Device 1 Wake Enable Bit OTG Wake Enable Bit Host/Device 2 Interrupt Enable Bit Halt Enable BitOTG Interrupt Enable Bit SPI Interrupt Enable Bit Timer 0 Interrupt Enable Bit Uart Interrupt Enable BitGpio Interrupt Enable Bit Timer 1 Interrupt Enable Bit LS Pull-up Enable Bit Port 2A Diagnostic Enable BitPort 1A Diagnostic Enable Bit Pull-down Enable Bit Reset Strobe Bit Timeout Flag BitLock Enable Bit WDT Enable Bit 0xC08A/0xC0AA Timer n Register R/WGeneral USB Registers USB Registers Register Name Address SIE1/SIE2 Resistors Function Select Enable Mode Select BitPort a Resistors Enable Bit USB Data Line Pull-up and Pull-down Resistors Mode Port n Arm Enable Bit Preamble Enable BitSync Enable Bit ISO Enable Bit Host 1 Count Register 0xC084 Host 2 Count Register 0xC0A4 Host n Address Register R/WHost n Count Register R/W NAK Flag Bit Error Flag BitUnderflow Flag Bit Stall Flag Bit PID Select ACK Flag BitHost n PID Register W PID Select Definition Host n Device Address Register W Host n Count Result Register R Port a Wake Interrupt Enable Bit Vbus Interrupt Enable BitID Interrupt Enable Bit SOF/EOP Interrupt Enable Bit Port a Wake Interrupt Flag Bit Vbus Interrupt Flag BitID Interrupt Flag Bit SOF/EOP Interrupt Flag Bit Host n SOF/EOP Counter Register R Host n SOF/EOP Count Register R/WCount Bits Count field sets the SOF/EOP counter duration Register Name Address Device 1/Device Host n Frame Register RUSB Device Only Registers Reserved USB Device Only Registers Enable Bit IN/OUT Ignore Enable BitStall Enable Bit NAK Interrupt Enable Bit Device n Endpoint n Count Register R/W Device n Endpoint n Address Register R/W OUT Exception Flag Bit Device n Endpoint n Status Register R/W Exception Flag Bit Setup Flag BitTimeout occurred Timeout condition did not occur Error occurred Error did not occur Device n Endpoint n Count Result Register Device n Endpoint n Count Result Register R/W EP7 Interrupt Enable Bit Device n Interrupt Enable Register R/WSOF/EOP Timeout Interrupt Enable Bit Reset Interrupt Enable Bit EP1 Interrupt Enable Bit EP5 Interrupt Enable Bit EP2 Interrupt Enable BitEP4 Interrupt Enable Bit EP3 Interrupt Enable Bit Device n Status Register R/W Device n Address Register W EP5 Interrupt Flag Bit Reset Interrupt Flag BitEP7 Interrupt Flag Bit EP6 Interrupt Flag Bit Device n SOF/EOP Count Register W SOF/EOP Timeout Flag BitSOF/EOP Timeout Interrupt Counter Bits Device n Frame Number Register R Vbus Discharge Enable Bit Vbus Pull-up Enable BitReceive Disable Bit Charge Pump Enable Bit Vbus Valid Flag Bit Write Protect Enable BitSAS Enable Bit Mode Select Definition Gpio Configuration 108 111 Reserved Interrupt 0 Polarity Select Bit HSS Enable BitSPI Enable Bit Interrupt 0 Enable Bit Gpio 0 Direction Register 0xC022 R/W Gpio 0 Input Data Register 0xC020 RGpio 1 Input Data Register 0xC026 R HSS Registers Register Name Address Gpio 1 Direction Register 0xC028 R/WHSS Registers RTS Polarity Select Bit Xoff Enable BitCTS Enable Bit Receive Interrupt Enable Bit Receive Packet Ready Flag Bit Packet Mode Select BitTransmit Ready Bit Receive Overflow Flag Bit HSS Data Register 0xC076 R/W HSS Transmit Gap Register 0xC074 R/WTransmit Gap Select Bits HSS Receive Counter Register 0xC07A R/W HSS Receive Address Register 0xC078 R/W HPI Registers Register Name Address HSS Transmit Address Register 0xC07C R/WHSS Transmit Counter Register 0xC07E R/W HPI Registers HPI Breakpoint Register 0x0140 R Vbus to HPI Enable BitID to HPI Enable Bit SOF/EOP2 to HPI Enable Bit Reset2 to HPI Enable Bit SOF/EOP2 to CPU Enable BitSOF/EOP1 to HPI Enable Bit SOF/EOP1 to CPU Enable Bit HPI Mailbox Register 0xC0C6 R/W SIEXmsg Register WSIE1msg Register SIE2msg Register Data Bits SOF/EOP2 Flag Bit Reset2 Flag BitVbus Flag Bit ID Flag Bit SPI Registers Register Name Address SPI Registers Reset1 Flag BitDone1 Flag Bit Mailbox Out Flag Bit Master Enable Bit 3Wire Enable BitPhase Select Bit Master Active Enable Bit Fifo Init Bit Byte Mode BitRead Enable Bit SCK Strobe Bit Receive Bit Length Bits Transmit Interrupt Enable BitTransfer Interrupt Enable Bit Fifo Error Flag Bit Transmit Interrupt Clear Bit CRC Mode Definition CRCMode CRC PolynomialTransmit Interrupt Flag Bit Transfer Interrupt Flag Bit One in CRC Bit CRC Enable BitCRC Clear Bit Receive CRC Bit SPI Transmit Count Register 0xC0DA R/W SPI Transmit Address Register 0xC0D8 R/W Uart Registers Register Name Address SPI Receive Address Register 0xC0DC R/WSPI Receive Count Register 0xC0DE R/W Uart Registers Uart Baud Select Definition Baud Rate DIV8 = Uart Enable BitScale Select Bit Baud Select Bits Uart Data Register 0xC0E4 R/W Transmit Full Bit Pin Descriptions Name Type Pin DiagramPin Descriptions A0 HPI A0 GPIO20 General Purpose IOA1 HPI A1 GPIO19 General Purpose IO Crystal Requirements XTALIN, Xtalout Booster Power Input 2.7V toAbsolute Maximum Ratings Operating Conditions DC Characteristics Reset Timing AC Timing Characteristics Parameter Description Min Typical Max Unit Clock TimingI2C Eeprom Timing HPI Host Port Interface Write Cycle Timing Read Cycle Time Document # 38-08014 Rev. *G Data Access Time, from HPInRD fallingHPI Host Port Interface Read Cycle Timing Read Pulse Width HSS Byte and Block Mode Receive HSS Byte Mode TransmitHSS Block Mode Transmit Hssrts Hsscts Hardware CTS/RTS Handshake Register Summary Register Summary GPIO31 GPIO30 GPIO29 SE0 SOF/EOP2 Ball 7.00 mm x 7.00 mm x 1.2 mm Fbga BA48 Package DiagramOrdering Information Ordering Information Ordering Code Package Type PB-Free Document History Issue Orig. Description of Change Date