CY7C67200
Host n Interrupt Enable Register [R/W]
•Host 1 Interrupt Enable Register 0xC08C
•Host 2 Interrupt Enable Register 0xC0AC
Figure 25. Host n Interrupt Enable Register
Bit # | 15 | 14 | 13 | 12 |
| 11 | 10 | 9 | 8 |
Field | VBUS | ID Interrupt |
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| Reserved |
| SOF/EOP | Reserved | |
Interrupt Enable | Enable |
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| Interrupt Enable |
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Read/Write | R/W | R/W | - | - |
| - | - | R/W | - |
Default | 0 | 0 | 0 | 0 |
| 0 | 0 | 0 | 0 |
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Bit # | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reserved | Port A | Reserved | Port A Connect |
| Reserved |
| Done |
Field |
| Wake Interrupt Enable |
| Change |
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| Interrupt Enable |
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| Interrupt Enable |
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Read/Write | - | R/W | - | R/W | - | - | - | R/W |
Default | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
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Register Description
The Host n Interrupt Enable register allows control over
In this register a bit set to ‘1’ enables the corresponding interrupt while ‘0’ disables the interrupt.
VBUS Interrupt Enable (Bit 15)
The VBUS Interrupt Enable bit enables or disables the OTG VBUS interrupt. When enabled this interrupt triggers on both the rising and falling edge of VBUS at the 4.4V status (only supported in Port 1A). This bit is only available for Host 1 and is a reserved bit in Host 2.
1:Enable VBUS interrupt
0:Disable VBUS interrupt
ID Interrupt Enable (Bit 14)
The ID Interrupt Enable bit enables or disables the OTG ID interrupt. When enabled this interrupt triggers on both the rising and falling edge of the OTG ID pin (only supported in Port 1A). This bit is only available for Host 1 and is a reserved bit in Host 2.
1:Enable ID interrupt
0:Disable ID interrupt
SOF/EOP Interrupt Enable (Bit 9)
The SOF/EOP Interrupt Enable bit enables or disables the SOF/EOP timer interrupt.
1:Enable SOF/EOP timer interrupt
0:Disable SOF/EOP timer interrupt
Port A Wake Interrupt Enable (Bit 6)
The Port A Wake Interrupt Enable bit enables or disables the remote wakeup interrupt for Port A.
1:Enable remote wakeup interrupt for Port A
0:Disable remote wakeup interrupt for Port A
Port A Connect Change Interrupt Enable (Bit 4)
The Port A Connect Change Interrupt Enable bit enables or disables the Connect Change interrupt on Port A. This interrupt triggers when either a device is inserted (SE0 state to J state) or a device is removed (J state to SE0 state).
1:Enable Connect Change interrupt
0:Disable Connect Change interrupt
Done Interrupt Enable (Bit 0)
The Done Interrupt Enable bit enables or disables the USB Transfer Done interrupt. The USB Transfer Done triggers when either the host responds with an ACK, or a device responds with any of the following: ACK, NAK, STALL, or Timeout. This interrupt is used for both Port A and Port B.
1:Enable USB Transfer Done interrupt
0:Disable USB Transfer Done interrupt
Reserved
All reserved bits must be written as ‘0’.
Document #: | Page 25 of 78 |
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