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Cypress CY7C67200 manual GPIO 1 Direction Register 0xC028 R/W

Models: CY7C67200

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GPIO 1 Direction Register [0xC028] [R/W]

CY7C67200

Register Description

The GPIO 0 Direction register controls the direction of the GPIO data pins (input/output). The GPIO 0 Direction register controls GPIO15 to GPIO0 while the GPIO 1 Direction register controls GPIO31 to GPIO19.

When any bit of this register is set to ‘1’, the corresponding GPIO data pin becomes an output. When any bit of this register is set to ‘0’, the corresponding GPIO data pin becomes an input.

Reserved

All reserved bits must be written as ‘0’.

GPIO 1 Direction Register [0xC028] [R/W]

Figure 47. GPIO 1 Direction Register

Bit #	15	14	13	12	11		10	9	8
Field	GPIO31	GPIO30	GPIO29			Reserved			GPIO24
Read/Write	R/W	R/W	R/W	R/W	R/W		R/W	R/W	R/W
Default	0	0	0	0	0		0	0	0

Bit #	7	6	5	4	3	2	1	0
Field	GPIO23	GPIO22	GPIO21	GPIO20	GPIO19		Reserved
Read/Write	R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W
Default	0	0	0	0	0	0	0	0

Register Description

The GPIO 1 Direction register controls the direction of the GPIO data pins (input/output). The GPIO 0 Direction register controls GPIO15 to GPIO0 while the GPIO 1 Direction register controls GPIO31 to GPIO19.

When any bit of this register is set to ‘1’, the corresponding GPIO data pin becomes an output. When any bit of this register is set to ‘0’, the corresponding GPIO data pin becomes an input.

Reserved

All reserved bits must be written as ‘0’.

HSS Registers

There are eight registers dedicated to HSS operation. Each of these registers are covered in this section and summarized in Table 31.

Table 31.HSS Registers

Register Name	Address	R/W
HSS Control Register	0xC070	R/W

HSS Baud Rate Register	0xC072	R/W

HSS Transmit Gap Register	0xC074	R/W

HSS Data Register	0xC076	R/W

HSS Receive Address Register	0xC078	R/W

HSS Receive Length Register	0xC07A	R/W

HSS Transmit Address Register	0xC07C	R/W

HSS Transmit Length Register	0xC07E	R/W

Document #: 38-08014 Rev. *G

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Cypress CY7C67200 manual GPIO 1 Direction Register 0xC028 R/W

Contents

CY7C67200 EZ-OTG FeaturesCY7C67200 Typical ApplicationsCY7C67200 IntroductionProcessor Core Functional Overview Interface DescriptionsOTG Pins USB FeaturesUSB Pins OTG FeaturesI2C EEPROM Pins UART FeaturesUART Pins I2C EEPROM FeaturesCY7C67200 HPI FeaturesHPI Pins CY7C67200CY7C67200 Charge Pump FeaturesCharge Pump Pins Booster PinsCY7C67200 Crystal PinsCoprocessor Mode Standalone ModePower Savings Mode Description Power Savings and Reset DescriptionMinimum Hardware Requirements for Standalone Mode - Peripheral Only Figure 5. Minimum Standalone Hardware Configuration - Peripheral Only0x0000 - 0x00FF 0x0100 - 0x011F 0x0120 - 0x013F LCP Variables USB Registers Slave Setup Packet BIOS StackMemory Map Internal MemoryCPU Flags Register 0xC000 R RegistersCY7C67200 Hardware Revision Register 0xC004 R Bank Register 0xC002 R/WCY7C67200 CY7C67200 CPU Speed Register 0xC008 R/WCY7C67200 Power Control Register 0xC00A R/WCY7C67200 Interrupt Enable Register 0xC00E R/WCY7C67200 Breakpoint Register 0xC014 R/WForce Select USB Diagnostic Register 0xC03C R/WCY7C67200 Pull-downStrobe Watchdog Timer Register 0xC00C R/WCY7C67200 LockCY7C67200 Timer n Register R/WUSB n Control Register R/W Resistors Enable0xC094/0xC0B4 CY7C67200Pull up/Pull down on D+ and 0xC090/0xC0B0Sync Host n Control Register R/WCY7C67200 SequenceHost n Count Register R/W Host n Address Register R/WCY7C67200 CY7C67200 Host n Endpoint Status Register RLength CY7C67200 Host n PID Register WHost n Device Address Register W Host n Count Result Register RCY7C67200 CY7C67200 Host n Interrupt Enable Register R/WPort A Connect CY7C67200 Host n Status Register R/WPort A Connect Host n SOF/EOP Counter Register R Host n SOF/EOP Count Register R/WCY7C67200 Device n Endpoint n Control Register R/W Host n Frame Register RCY7C67200 CY7C67200 Device n Endpoint n Count Register R/W Device n Endpoint n Address Register R/WCY7C67200 Setup Device n Endpoint n Status Register R/WCY7C67200 Page 32 of CY7C67200CY7C67200 Device n Endpoint n Count Result Register R/WInterrupt Enable Device n Interrupt Enable Register R/WCY7C67200 Page 35 of CY7C67200Device n Status Register R/W Device n Address Register WCY7C67200 Page 37 of CY7C67200Device n SOF/EOP Count Register W Device n Frame Number Register RCY7C67200 CY7C67200 OTG Control Register 0xC098 R/WC098H CY7C67200 GPIO Control Register 0xC006 R/WGPIO 1 Output Data Register 0xC024 R/W GPIO 0 Output Data Register 0xC01E R/WCY7C67200 CY7C67200 GPIO 0 Input Data Register 0xC020 RGPIO 1 Input Data Register 0xC026 R GPIO 0 Direction Register 0xC022 R/WCY7C67200 GPIO 1 Direction Register 0xC028 R/WCY7C67200 HSS Control Register 0xC070 R/WCY7C67200 HSS Baud Rate Register 0xC072 R/WHSS Data Register 0xC076 R/W HSS Transmit Gap Register 0xC074 R/WCY7C67200 HSS Receive Counter Register 0xC07A R/W HSS Receive Address Register 0xC078 R/WCY7C67200 HSS Transmit Counter Register 0xC07E R/W HSS Transmit Address Register 0xC07C R/WCY7C67200 Interrupt Routing Register 0x0142 R HPI Breakpoint Register 0x0140 RCY7C67200 CY7C67200 SOF/EOP2 to CPU Enable BitHPI Mailbox Register 0xC0C6 R/W SIEXmsg Register WCY7C67200 CY7C67200 HPI Status Port HPI RCY7C67200 SPI Configuration Register 0xC0C8 R/WCY7C67200 3Wire Enable BitReceive Bit Length SPI Control Register 0xC0CA R/WCY7C67200 StrobeSPI Status Register 0xC0CE R SPI Interrupt Enable Register 0xC0CC R/WCY7C67200 SPI CRC Control Register 0xC0D2 R/W SPI Interrupt Clear Register 0xC0D0 WCY7C67200 SPI Data Register 0xC0D6 R/W SPI CRC Value Register 0xC0D4 R/WCY7C67200 SPI Transmit Count Register 0xC0DA R/W SPI Transmit Address Register 0xC0D8 R/WCY7C67200 SPI Receive Count Register 0xC0DE R/W SPI Receive Address Register 0xC0DC R/WCY7C67200 UART Status Register 0xC0E2 R UART Control Register 0xC0E0 R/WCY7C67200 CY7C67200 UART Data Register 0xC0E4 R/WPin Descriptions Pin DiagramCY7C67200 Type CY7C67200Table 38.Pin Descriptions continued NameCY7C67200 Absolute Maximum RatingsOperating Conditions Crystal Requirements XTALIN, XTALOUTCY7C67200 DC CharacteristicsCY7C67200 AC Timing CharacteristicsReset Timing nRESET nRD or nWRL or nWRHCY7C67200 Clock Timing1. I2C EEPROM Bus Timing - Serial I/O XTALINtCYC ADDR nCS nWR nRD DoutCY7C67200 tASU tCSSUCY7C67200 ADDRHSS BYTE and BLOCK Mode Receive CY7C67200HSS BYTE Mode Transmit HSS Block Mode TransmitHardware CTS/RTS Handshake CY7C67200Page 72 of CY7C67200 Register SummaryDefault High Default Low+ Feedback Default HighDefault Low CY7C67200+ Feedback Default HighDefault Low CY7C67200+ Feedback Default HighDefault Low CY7C67200Table 43.Ordering Information Package DiagramOrdering Information CY7C67200Mode” Document History Page“Interrupt Enable Register 0xC00E R/W” CY7C67200