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Cypress CY7C67200 manual GPIO 0 Input Data Register 0xC020 R, GPIO 1 Input Data Register 0xC026 R

Models: CY7C67200

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GPIO 0 Input Data Register [0xC020] [R]

CY7C67200

Writing a 1 to any bit will output a high voltage on the corresponding GPIO pin.

Reserved

All reserved bits must be written as ‘0’.

GPIO 0 Input Data Register [0xC020] [R]

Figure 44. GPIO 0 Input Data Register

Bit #	15	14	13	12	11	10	9	8
Field	GPIO15	GPIO14	GPIO13	GPIO12	GPIO11	GPIO10	GPIO9	GPIO8
Read/Write	R	R	R	R	R	R	R	R
Default	0	0	0	0	0	0	0	0

Bit #	7	6	5	4	3	2	1	0
Field	GPIO7	GPIO6	GPIO5	GPIO4	GPIO3	GPIO2	GPIO1	GPIO0
Read/Write	R	R	R	R	R	R	R	R
Default	0	0	0	0	0	0	0	0

Register Description

The GPIO 0 Input Data register reads the input data of the GPIO pins. The GPIO 0 Input Data register reads from GPIO15 to GPIO0 while the GPIO 1 Input Data register reads from GPIO31 to GPIO19.

Every bit represents the voltage of that GPIO pin.

GPIO 1 Input Data Register [0xC026] [R]

Figure 45. GPIO 1 Input Data Register

Bit #	15	14	13	12	11		10	9	8
Field	GPIO31	GPIO30	GPIO29			Reserved			GPIO24
Read/Write	R	R	R	-	-		-	-	R
Default	0	0	0	0	0		0	0	0

Bit #	7	6	5	4	3	2	1	0
Field	GPIO23	GPIO22	GPIO21	GPIO20	GPIO19		Reserved
Read/Write	R	R	R	R	R	-	-	-
Default	0	0	0	0	0	0	0	0

Register Description

The GPIO 1 Input Data register reads the input data of the GPIO pins. The GPIO 0 Input Data register reads from GPIO15 to GPIO0 while the GPIO 1 Input Data register reads from GPIO31 to GPIO19.

Every bit represents the voltage of that GPIO pin.

GPIO 0 Direction Register [0xC022] [R/W]

Figure 46. GPIO 0 Direction Register

Bit #	15	14	13	12	11	10	9	8
Field	GPIO15	GPIO14	GPIO13	GPIO12	GPIO11	GPIO10	GPIO9	GPIO8
Read/Write	R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W
Default	0	0	0	0	0	0	0	0

Bit #	7	6	5	4	3	2	1	0
Field	GPIO7	GPIO6	GPIO5	GPIO4	GPIO3	GPIO2	GPIO1	GPIO0
Read/Write	R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W
Default	0	0	0	0	0	0	0	0

Document #: 38-08014 Rev. *G

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Cypress CY7C67200 manual GPIO 0 Input Data Register 0xC020 R, GPIO 1 Input Data Register 0xC026 R

Contents

Typical Applications EZ-OTG FeaturesCY7C67200 CY7C67200Interface Descriptions IntroductionProcessor Core Functional Overview CY7C67200OTG Features USB FeaturesUSB Pins OTG PinsI2C EEPROM Features UART FeaturesUART Pins I2C EEPROM PinsCY7C67200 HPI FeaturesHPI Pins CY7C67200Booster Pins Charge Pump FeaturesCharge Pump Pins CY7C67200Standalone Mode Crystal PinsCoprocessor Mode CY7C67200Figure 5. Minimum Standalone Hardware Configuration - Peripheral Only Power Savings and Reset DescriptionMinimum Hardware Requirements for Standalone Mode - Peripheral Only Power Savings Mode DescriptionInternal Memory LCP Variables USB Registers Slave Setup Packet BIOS StackMemory Map 0x0000 - 0x00FF 0x0100 - 0x011F 0x0120 - 0x013FRegisters CPU Flags Register 0xC000 RCY7C67200 Bank Register 0xC002 R/W Hardware Revision Register 0xC004 RCY7C67200 CPU Speed Register 0xC008 R/W CY7C67200Power Control Register 0xC00A R/W CY7C67200Interrupt Enable Register 0xC00E R/W CY7C67200Breakpoint Register 0xC014 R/W CY7C67200Pull-down USB Diagnostic Register 0xC03C R/WCY7C67200 Force SelectLock Watchdog Timer Register 0xC00C R/WCY7C67200 StrobeResistors Enable Timer n Register R/WUSB n Control Register R/W CY7C672000xC090/0xC0B0 CY7C67200Pull up/Pull down on D+ and 0xC094/0xC0B4Sequence Host n Control Register R/WCY7C67200 SyncHost n Address Register R/W Host n Count Register R/WCY7C67200 Host n Endpoint Status Register R CY7C67200Length Host n PID Register W CY7C67200Host n Count Result Register R Host n Device Address Register WCY7C67200 Host n Interrupt Enable Register R/W CY7C67200Port A Connect Host n Status Register R/W CY7C67200Port A Connect Host n SOF/EOP Count Register R/W Host n SOF/EOP Counter Register RCY7C67200 Host n Frame Register R Device n Endpoint n Control Register R/WCY7C67200 CY7C67200 Device n Endpoint n Address Register R/W Device n Endpoint n Count Register R/WCY7C67200 Device n Endpoint n Status Register R/W SetupCY7C67200 CY7C67200 Page 32 ofDevice n Endpoint n Count Result Register R/W CY7C67200Device n Interrupt Enable Register R/W Interrupt EnableCY7C67200 CY7C67200 Page 35 ofDevice n Address Register W Device n Status Register R/WCY7C67200 CY7C67200 Page 37 ofDevice n Frame Number Register R Device n SOF/EOP Count Register WCY7C67200 OTG Control Register 0xC098 R/W CY7C67200C098H GPIO Control Register 0xC006 R/W CY7C67200GPIO 0 Output Data Register 0xC01E R/W GPIO 1 Output Data Register 0xC024 R/WCY7C67200 GPIO 0 Direction Register 0xC022 R/W GPIO 0 Input Data Register 0xC020 RGPIO 1 Input Data Register 0xC026 R CY7C67200GPIO 1 Direction Register 0xC028 R/W CY7C67200HSS Control Register 0xC070 R/W CY7C67200HSS Baud Rate Register 0xC072 R/W CY7C67200HSS Transmit Gap Register 0xC074 R/W HSS Data Register 0xC076 R/WCY7C67200 HSS Receive Address Register 0xC078 R/W HSS Receive Counter Register 0xC07A R/WCY7C67200 HSS Transmit Address Register 0xC07C R/W HSS Transmit Counter Register 0xC07E R/WCY7C67200 HPI Breakpoint Register 0x0140 R Interrupt Routing Register 0x0142 RCY7C67200 SOF/EOP2 to CPU Enable Bit CY7C67200SIEXmsg Register W HPI Mailbox Register 0xC0C6 R/WCY7C67200 HPI Status Port HPI R CY7C67200SPI Configuration Register 0xC0C8 R/W CY7C672003Wire Enable Bit CY7C67200Strobe SPI Control Register 0xC0CA R/WCY7C67200 Receive Bit LengthSPI Interrupt Enable Register 0xC0CC R/W SPI Status Register 0xC0CE RCY7C67200 SPI Interrupt Clear Register 0xC0D0 W SPI CRC Control Register 0xC0D2 R/WCY7C67200 SPI CRC Value Register 0xC0D4 R/W SPI Data Register 0xC0D6 R/WCY7C67200 SPI Transmit Address Register 0xC0D8 R/W SPI Transmit Count Register 0xC0DA R/WCY7C67200 SPI Receive Address Register 0xC0DC R/W SPI Receive Count Register 0xC0DE R/WCY7C67200 UART Control Register 0xC0E0 R/W UART Status Register 0xC0E2 RCY7C67200 UART Data Register 0xC0E4 R/W CY7C67200Pin Diagram Pin DescriptionsCY7C67200 Name CY7C67200Table 38.Pin Descriptions continued TypeCrystal Requirements XTALIN, XTALOUT Absolute Maximum RatingsOperating Conditions CY7C67200DC Characteristics CY7C67200nRESET nRD or nWRL or nWRH AC Timing CharacteristicsReset Timing CY7C67200XTALIN Clock Timing1. I2C EEPROM Bus Timing - Serial I/O CY7C67200tASU tCSSU ADDR nCS nWR nRD DoutCY7C67200 tCYCADDR CY7C67200HSS Block Mode Transmit CY7C67200HSS BYTE Mode Transmit HSS BYTE and BLOCK Mode ReceiveCY7C67200 Hardware CTS/RTS HandshakePage 72 of Default Low Register SummaryDefault High CY7C67200CY7C67200 Default HighDefault Low + FeedbackCY7C67200 Default HighDefault Low + FeedbackCY7C67200 Default HighDefault Low + FeedbackCY7C67200 Package DiagramOrdering Information Table 43.Ordering InformationCY7C67200 Document History Page“Interrupt Enable Register 0xC00E R/W” Mode”