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Cypress CY7C67200 manual EZ-OTG Features, Typical Applications, EZ-OTG Programmable USB On-The-Go

Models: CY7C67200

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CY7C67200

CY7C67200

EZ-OTG™ Programmable USB

On-The-Go

EZ-OTG Features

•Single-chip programmable USB dual-role (Host/Peripheral) controller with two configurable Serial Interface Engines (SIEs) and two USB ports

•Supports USB OTG protocol

•On-chip 48-MHz 16-bit processor with dynamically switchable clock speed

•Configurable IO block supports a variety of IO options or up to 25 bits of General Purpose IO (GPIO)

•4K × 16 internal mask ROM contains built-in BIOS that supports a communication-ready state with access to I2C™ EEPROM interface, external ROM, UART, or USB

•8K x 16 internal RAM for code and data buffering

•16-bit parallel host port interface (HPI) with DMA/Mailbox data path for an external processor to directly access all on-chip memory and control on-chip SIEs

•Fast serial port supports from 9600 baud to 2.0M baud

•SPI supports both master and slave

•Supports 12 MHz external crystal or clock

•2.7V to 3.6V power supply voltage

•Package option: 48-pin FBGA

Typical Applications

EZ-OTG is a very powerful and flexible dual-role USB controller that supports a wide variety of applications. It is primarily intended to enable USB OTG capability in applica- tions such as:

•Cellular phones

•PDAs and pocket PCs

•Video and digital still cameras

•MP3 players

•Mass storage devices

Block Diagram
CY7C67200		CY7C67200
		CY7C67200
nRESET	Control		Timer 0	Timer 1
nRESET	Control
		Watchdog		CY16	UART I/F
				CY16
Vbus, ID			16-bit RISC CORE		I2C	PINS
					I2C
					EEPROM I/F

	OTG					INPUT/OUTPUT
D+,D-		USB-A				INPUT/OUTPUT
D+,D-		USB-A
HOST/		SIE1			HSS I/F
		SIE1

Peripheral							GPIO [24:0]
USB Ports							GPIO [24:0]
USB Ports					SPI I/F
					SPI I/F	SHARED
D+,D-		USB-A	4Kx16	8Kx16		SHARED
D+,D-		USB-A	4Kx16	8Kx16
		SIE2	ROM BIOS	RAM	HPI I/F
		SIE2			HPI I/F
X1		Mobile			GPIO
	PLL	Mobile
		Power
X2		Power
		Booster

Cypress Semiconductor Corporation	• 198 Champion Court • San Jose, CA 95134-1709	•	408-943-2600
Document #: 38-08014 Rev. *G	Revised November 14, 2006

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Cypress CY7C67200 manual EZ-OTG Features, Typical Applications, EZ-OTG Programmable USB On-The-Go, Block Diagram

Contents

CY7C67200 EZ-OTG FeaturesTypical Applications CY7C67200Processor Core Functional Overview IntroductionInterface Descriptions CY7C67200USB Pins USB FeaturesOTG Features OTG PinsUART Pins UART FeaturesI2C EEPROM Features I2C EEPROM PinsHPI Pins HPI FeaturesCY7C67200 CY7C67200Charge Pump Pins Charge Pump FeaturesBooster Pins CY7C67200Coprocessor Mode Crystal PinsStandalone Mode CY7C67200Minimum Hardware Requirements for Standalone Mode - Peripheral Only Power Savings and Reset DescriptionFigure 5. Minimum Standalone Hardware Configuration - Peripheral Only Power Savings Mode DescriptionMemory Map LCP Variables USB Registers Slave Setup Packet BIOS StackInternal Memory 0x0000 - 0x00FF 0x0100 - 0x011F 0x0120 - 0x013FCPU Flags Register 0xC000 R RegistersCY7C67200 Hardware Revision Register 0xC004 R Bank Register 0xC002 R/WCY7C67200 CY7C67200 CPU Speed Register 0xC008 R/WCY7C67200 Power Control Register 0xC00A R/WCY7C67200 Interrupt Enable Register 0xC00E R/WCY7C67200 Breakpoint Register 0xC014 R/WCY7C67200 USB Diagnostic Register 0xC03C R/WPull-down Force SelectCY7C67200 Watchdog Timer Register 0xC00C R/WLock StrobeUSB n Control Register R/W Timer n Register R/WResistors Enable CY7C67200Pull up/Pull down on D+ and CY7C672000xC090/0xC0B0 0xC094/0xC0B4CY7C67200 Host n Control Register R/WSequence SyncHost n Count Register R/W Host n Address Register R/WCY7C67200 CY7C67200 Host n Endpoint Status Register RLength CY7C67200 Host n PID Register WHost n Device Address Register W Host n Count Result Register RCY7C67200 CY7C67200 Host n Interrupt Enable Register R/WPort A Connect CY7C67200 Host n Status Register R/WPort A Connect Host n SOF/EOP Counter Register R Host n SOF/EOP Count Register R/WCY7C67200 Device n Endpoint n Control Register R/W Host n Frame Register RCY7C67200 CY7C67200 Device n Endpoint n Count Register R/W Device n Endpoint n Address Register R/WCY7C67200 Setup Device n Endpoint n Status Register R/WCY7C67200 Page 32 of CY7C67200CY7C67200 Device n Endpoint n Count Result Register R/WInterrupt Enable Device n Interrupt Enable Register R/WCY7C67200 Page 35 of CY7C67200Device n Status Register R/W Device n Address Register WCY7C67200 Page 37 of CY7C67200Device n SOF/EOP Count Register W Device n Frame Number Register RCY7C67200 CY7C67200 OTG Control Register 0xC098 R/WC098H CY7C67200 GPIO Control Register 0xC006 R/WGPIO 1 Output Data Register 0xC024 R/W GPIO 0 Output Data Register 0xC01E R/WCY7C67200 GPIO 1 Input Data Register 0xC026 R GPIO 0 Input Data Register 0xC020 RGPIO 0 Direction Register 0xC022 R/W CY7C67200CY7C67200 GPIO 1 Direction Register 0xC028 R/WCY7C67200 HSS Control Register 0xC070 R/WCY7C67200 HSS Baud Rate Register 0xC072 R/WHSS Data Register 0xC076 R/W HSS Transmit Gap Register 0xC074 R/WCY7C67200 HSS Receive Counter Register 0xC07A R/W HSS Receive Address Register 0xC078 R/WCY7C67200 HSS Transmit Counter Register 0xC07E R/W HSS Transmit Address Register 0xC07C R/WCY7C67200 Interrupt Routing Register 0x0142 R HPI Breakpoint Register 0x0140 RCY7C67200 CY7C67200 SOF/EOP2 to CPU Enable BitHPI Mailbox Register 0xC0C6 R/W SIEXmsg Register WCY7C67200 CY7C67200 HPI Status Port HPI RCY7C67200 SPI Configuration Register 0xC0C8 R/WCY7C67200 3Wire Enable BitCY7C67200 SPI Control Register 0xC0CA R/WStrobe Receive Bit LengthSPI Status Register 0xC0CE R SPI Interrupt Enable Register 0xC0CC R/WCY7C67200 SPI CRC Control Register 0xC0D2 R/W SPI Interrupt Clear Register 0xC0D0 WCY7C67200 SPI Data Register 0xC0D6 R/W SPI CRC Value Register 0xC0D4 R/WCY7C67200 SPI Transmit Count Register 0xC0DA R/W SPI Transmit Address Register 0xC0D8 R/WCY7C67200 SPI Receive Count Register 0xC0DE R/W SPI Receive Address Register 0xC0DC R/WCY7C67200 UART Status Register 0xC0E2 R UART Control Register 0xC0E0 R/WCY7C67200 CY7C67200 UART Data Register 0xC0E4 R/WPin Descriptions Pin DiagramCY7C67200 Table 38.Pin Descriptions continued CY7C67200Name TypeOperating Conditions Absolute Maximum RatingsCrystal Requirements XTALIN, XTALOUT CY7C67200CY7C67200 DC CharacteristicsReset Timing AC Timing CharacteristicsnRESET nRD or nWRL or nWRH CY7C672001. I2C EEPROM Bus Timing - Serial I/O Clock TimingXTALIN CY7C67200CY7C67200 ADDR nCS nWR nRD DouttASU tCSSU tCYCCY7C67200 ADDRHSS BYTE Mode Transmit CY7C67200HSS Block Mode Transmit HSS BYTE and BLOCK Mode ReceiveHardware CTS/RTS Handshake CY7C67200Page 72 of Default High Register SummaryDefault Low CY7C67200Default Low Default HighCY7C67200 + FeedbackDefault Low Default HighCY7C67200 + FeedbackDefault Low Default HighCY7C67200 + FeedbackOrdering Information Package DiagramCY7C67200 Table 43.Ordering Information“Interrupt Enable Register 0xC00E R/W” Document History PageCY7C67200 Mode”