EZ-OTG Features, Typical Applications | Cypress CY7C67200 instruction

CY7C67200

EZ-OTG™ Programmable USB

On-The-Go

EZ-OTG Features

•Single-chip programmable USB dual-role (Host/Peripheral) controller with two configurable Serial Interface Engines (SIEs) and two USB ports

•Supports USB OTG protocol

•On-chip 48-MHz 16-bit processor with dynamically switchable clock speed

•Configurable IO block supports a variety of IO options or up to 25 bits of General Purpose IO (GPIO)

•4K × 16 internal mask ROM contains built-in BIOS that supports a communication-ready state with access to I2C™ EEPROM interface, external ROM, UART, or USB

•8K x 16 internal RAM for code and data buffering

•16-bit parallel host port interface (HPI) with DMA/Mailbox data path for an external processor to directly access all on-chip memory and control on-chip SIEs

•Fast serial port supports from 9600 baud to 2.0M baud

•SPI supports both master and slave

•Supports 12 MHz external crystal or clock

•2.7V to 3.6V power supply voltage

•Package option: 48-pin FBGA

Typical Applications

EZ-OTG is a very powerful and flexible dual-role USB controller that supports a wide variety of applications. It is primarily intended to enable USB OTG capability in applica- tions such as:

•Cellular phones

•PDAs and pocket PCs

•Video and digital still cameras

•MP3 players

•Mass storage devices

Block Diagram
CY7C67200		CY7C67200
		CY7C67200
nRESET	Control		Timer 0	Timer 1
nRESET	Control
		Watchdog		CY16	UART I/F
				CY16
Vbus, ID			16-bit RISC CORE		I2C	PINS
					I2C
					EEPROM I/F

	OTG					INPUT/OUTPUT
D+,D-		USB-A				INPUT/OUTPUT
D+,D-		USB-A
HOST/		SIE1			HSS I/F
		SIE1

Peripheral							GPIO [24:0]
USB Ports							GPIO [24:0]
USB Ports					SPI I/F
					SPI I/F	SHARED
D+,D-		USB-A	4Kx16	8Kx16		SHARED
D+,D-		USB-A	4Kx16	8Kx16
		SIE2	ROM BIOS	RAM	HPI I/F
		SIE2			HPI I/F
X1		Mobile			GPIO
	PLL	Mobile
		Power
X2		Power
		Booster

Cypress Semiconductor Corporation	• 198 Champion Court • San Jose, CA 95134-1709	•	408-943-2600
Document #: 38-08014 Rev. *G	Revised November 14, 2006

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Cypress CY7C67200 manual EZ-OTG Features, Typical Applications, CY16, Cypress Semiconductor Corporation

Contents

Typical Applications EZ-OTG FeaturesCY7C67200 CY16 Processor Core Functional Overview IntroductionInterface Descriptions OTG Interface Pins Pin Name Pin Number USB Interface Pins Pin Name Pin NumberUSB Interface OTG Interface SPI Interface Pins Pin Name Pin Number I2C Eeprom Interface Pins Pin Name Pin NumberHSS Interface Pins Pin Name Pin Number Serial Peripheral Interface Host Port Interface HPI HPI Interface Pins 1 Pin Name Pin NumberHPI Addressing HPI A10 Charge Pump Interface Booster Interface Charge Pump Interface Pins Pin Name Pin NumberCrystal Interface Boot Configuration Interface Crystal Pins Pin Name Pin NumberBoot Mode Pin Power Savings Mode Description Power Savings and Reset DescriptionSleep Memory Map Registers Bank Register Example Hex Value Binary Value Bank Register 0xC002 R/WReserved Hardware Revision Register 0xC004 R CPU Speed Definition Processor Speed CPU Speed Register 0xC008 R/W Host/Device 1 Wake Enable Bit Host/Device 2 Wake Enable BitOTG Wake Enable Bit HSS Wake Enable Bit OTG Interrupt Enable Bit Halt Enable BitSPI Interrupt Enable Bit Host/Device 2 Interrupt Enable Bit Gpio Interrupt Enable Bit Uart Interrupt Enable BitTimer 1 Interrupt Enable Bit Timer 0 Interrupt Enable Bit Port 1A Diagnostic Enable Bit Port 2A Diagnostic Enable BitPull-down Enable Bit LS Pull-up Enable Bit Lock Enable Bit Timeout Flag BitWDT Enable Bit Reset Strobe Bit General USB Registers Timer n Register R/WUSB Registers Register Name Address SIE1/SIE2 0xC08A/0xC0AA Port a Resistors Enable Bit Mode Select BitUSB Data Line Pull-up and Pull-down Resistors Mode Port n Resistors Function Select Enable Sync Enable Bit Preamble Enable BitISO Enable Bit Arm Enable Bit Host n Count Register R/W Host n Address Register R/WHost 1 Count Register 0xC084 Host 2 Count Register 0xC0A4 Underflow Flag Bit Error Flag BitStall Flag Bit NAK Flag Bit Host n PID Register W ACK Flag BitPID Select Definition PID Select Host n Device Address Register W Host n Count Result Register R ID Interrupt Enable Bit Vbus Interrupt Enable BitSOF/EOP Interrupt Enable Bit Port a Wake Interrupt Enable Bit ID Interrupt Flag Bit Vbus Interrupt Flag BitSOF/EOP Interrupt Flag Bit Port a Wake Interrupt Flag Bit Count Bits Count field sets the SOF/EOP counter duration Host n SOF/EOP Count Register R/WHost n SOF/EOP Counter Register R USB Device Only Registers Reserved Host n Frame Register RUSB Device Only Registers Register Name Address Device 1/Device Stall Enable Bit IN/OUT Ignore Enable BitNAK Interrupt Enable Bit Enable Bit Device n Endpoint n Count Register R/W Device n Endpoint n Address Register R/W OUT Exception Flag Bit Device n Endpoint n Status Register R/W Timeout occurred Timeout condition did not occur Setup Flag BitError occurred Error did not occur Exception Flag Bit Device n Endpoint n Count Result Register Device n Endpoint n Count Result Register R/W SOF/EOP Timeout Interrupt Enable Bit Device n Interrupt Enable Register R/WReset Interrupt Enable Bit EP7 Interrupt Enable Bit EP4 Interrupt Enable Bit EP5 Interrupt Enable Bit EP2 Interrupt Enable BitEP3 Interrupt Enable Bit EP1 Interrupt Enable Bit Device n Status Register R/W Device n Address Register W EP7 Interrupt Flag Bit Reset Interrupt Flag BitEP6 Interrupt Flag Bit EP5 Interrupt Flag Bit SOF/EOP Timeout Interrupt Counter Bits SOF/EOP Timeout Flag BitDevice n Frame Number Register R Device n SOF/EOP Count Register W Receive Disable Bit Vbus Pull-up Enable BitCharge Pump Enable Bit Vbus Discharge Enable Bit SAS Enable Bit Write Protect Enable BitMode Select Definition Gpio Configuration 108 111 Reserved Vbus Valid Flag Bit SPI Enable Bit HSS Enable BitInterrupt 0 Enable Bit Interrupt 0 Polarity Select Bit Gpio 1 Input Data Register 0xC026 R Gpio 0 Input Data Register 0xC020 RGpio 0 Direction Register 0xC022 R/W HSS Registers Gpio 1 Direction Register 0xC028 R/WHSS Registers Register Name Address CTS Enable Bit Xoff Enable BitReceive Interrupt Enable Bit RTS Polarity Select Bit Transmit Ready Bit Packet Mode Select BitReceive Overflow Flag Bit Receive Packet Ready Flag Bit Transmit Gap Select Bits HSS Transmit Gap Register 0xC074 R/WHSS Data Register 0xC076 R/W HSS Receive Counter Register 0xC07A R/W HSS Receive Address Register 0xC078 R/W HSS Transmit Counter Register 0xC07E R/W HSS Transmit Address Register 0xC07C R/WHPI Registers HPI Registers Register Name Address ID to HPI Enable Bit Vbus to HPI Enable BitSOF/EOP2 to HPI Enable Bit HPI Breakpoint Register 0x0140 R SOF/EOP1 to HPI Enable Bit SOF/EOP2 to CPU Enable BitSOF/EOP1 to CPU Enable Bit Reset2 to HPI Enable Bit SIE1msg Register SIE2msg Register SIEXmsg Register WData Bits HPI Mailbox Register 0xC0C6 R/W Vbus Flag Bit Reset2 Flag BitID Flag Bit SOF/EOP2 Flag Bit Done1 Flag Bit SPI Registers Reset1 Flag BitMailbox Out Flag Bit SPI Registers Register Name Address Phase Select Bit 3Wire Enable BitMaster Active Enable Bit Master Enable Bit Read Enable Bit Byte Mode BitSCK Strobe Bit Fifo Init Bit Transfer Interrupt Enable Bit Transmit Interrupt Enable BitFifo Error Flag Bit Receive Bit Length Bits Transmit Interrupt Flag Bit CRC Mode Definition CRCMode CRC PolynomialTransfer Interrupt Flag Bit Transmit Interrupt Clear Bit CRC Clear Bit CRC Enable BitReceive CRC Bit One in CRC Bit SPI Transmit Count Register 0xC0DA R/W SPI Transmit Address Register 0xC0D8 R/W SPI Receive Count Register 0xC0DE R/W SPI Receive Address Register 0xC0DC R/WUart Registers Uart Registers Register Name Address Scale Select Bit Uart Enable BitBaud Select Bits Uart Baud Select Definition Baud Rate DIV8 = Uart Data Register 0xC0E4 R/W Transmit Full Bit Pin Descriptions Pin DiagramPin Descriptions Name Type A1 HPI A1 GPIO20 General Purpose IOGPIO19 General Purpose IO A0 HPI A0 Absolute Maximum Ratings Booster Power Input 2.7V toOperating Conditions Crystal Requirements XTALIN, Xtalout DC Characteristics Reset Timing AC Timing Characteristics I2C Eeprom Timing Clock TimingParameter Description Min Typical Max Unit HPI Host Port Interface Write Cycle Timing HPI Host Port Interface Read Cycle Timing Data Access Time, from HPInRD fallingRead Pulse Width Read Cycle Time Document # 38-08014 Rev. *G HSS Block Mode Transmit HSS Byte Mode TransmitHSS Byte and Block Mode Receive Hssrts Hsscts Hardware CTS/RTS Handshake Register Summary Register Summary GPIO31 GPIO30 GPIO29 SE0 SOF/EOP2 Ordering Information Package DiagramOrdering Information Ordering Code Package Type PB-Free Ball 7.00 mm x 7.00 mm x 1.2 mm Fbga BA48 Document History Issue Orig. Description of Change Date