Manuals / Cypress / Computer Equipment / Computer Drive

Cypress CY7C67200 manual HSS BYTE Mode Transmit, HSS Block Mode Transmit, HSSTxD, Page 71 of

Models: CY7C67200

1 78

Download 78 pages 5 Kb

Page 71

HSS BYTE Mode Transmit

CY7C67200

HSS BYTE Mode Transmit

qt_clk

CPU_A[2:0]

CPUHSS_cs

CPU_wr

TxRdy flag

HSS_TxD

Byte transmit triggered by a CPU write to the HSS_TxData register

CPU may start another BYTE

transmit right after TxRdy

goes high

BT

BT

bit 1

bit 2

bit 3

bit 4

bit 5

bit 6

bit 7

stop bit start bit

start bit

bit 0

TxRdy low to start bit delay:

start of last data bit to TxRdy high:

programmable

0 min, 4 T max.

0 min, BT max when starting from IDEL.

1 or 2 stop bits.

(T is qt_clk period)

For back to back transmit, new START Bit

1 stop bit shown.

begins immediately following previous STOP bit.

(BT = bit period)

qt_clk, CPU_A, CPUHSS_cs, CPU_wr are internal signals, included in the diagram to illustrate relationship between CPU opera- tions and HSS port operations.

Bit 0 is LSB of data byte. Data bits are HIGH true: HSS_TxD HIGH = data bit value ‘1’. BT = bit time = 1/baud rate.

HSS Block Mode Transmit

BT

HSS_TxD

t GAP

BLOCK mode transmit timing is similar to BYTE mode, except the STOP bit time is controlled by the HSS_GAP value.

The BLOCK mode STOP bit time, tGAP = (HSS_GAP – 9) BT, where BT is the bit time, and HSS_GAP is the content of the HSS Transmit Gap register 90xC074].

The default tGAP is 2 BT. BT = bit time = 1/baud rate.

HSS BYTE and BLOCK Mode Receive

HSS_RxD

BT +/- 5%							received byte added to
							received byte added to
	BT +/- 5%						receive FIFO during the final data bit time
start bit	bit 0	bit 1	bit 2	bit 3	bit 4	bit 5	bit 6	bit 7	stop bit	start bit
				10 BT +/- 5%

Receive data arrives asynchronously relative to the internal clock.

Incoming data bit rate may deviate from the programmed baud rate clock by as much as ±5% (with HSS_RATE value of 23 or higher).

BYTE mode received bytes are buffered in a FIFO. The FIFO not empty condition becomes the RxRdy flag. BLOCK mode received bytes are written directly to the memory system.

Bit 0 is LSB of data byte. Data bits are HIGH true: HSS_RxD HIGH = data bit value ‘1’. BT = bit time = 1/baud rate.

Document #: 38-08014 Rev. *G

Page 71 of 78

[+] Feedback

Image 71

Cypress CY7C67200 HSS BYTE Mode Transmit, HSS Block Mode Transmit, HSS BYTE and BLOCK Mode Receive, HSSTxD, Page 71 of

Contents

CY7C67200 EZ-OTG FeaturesCY7C67200 Typical ApplicationsCY7C67200 IntroductionProcessor Core Functional Overview Interface DescriptionsOTG Pins USB FeaturesUSB Pins OTG FeaturesI2C EEPROM Pins UART FeaturesUART Pins I2C EEPROM FeaturesCY7C67200 HPI FeaturesHPI Pins CY7C67200CY7C67200 Charge Pump FeaturesCharge Pump Pins Booster PinsCY7C67200 Crystal PinsCoprocessor Mode Standalone ModePower Savings Mode Description Power Savings and Reset DescriptionMinimum Hardware Requirements for Standalone Mode - Peripheral Only Figure 5. Minimum Standalone Hardware Configuration - Peripheral Only0x0000 - 0x00FF 0x0100 - 0x011F 0x0120 - 0x013F LCP Variables USB Registers Slave Setup Packet BIOS StackMemory Map Internal MemoryCY7C67200 RegistersCPU Flags Register 0xC000 R CY7C67200 Bank Register 0xC002 R/WHardware Revision Register 0xC004 R CY7C67200 CPU Speed Register 0xC008 R/WCY7C67200 Power Control Register 0xC00A R/WCY7C67200 Interrupt Enable Register 0xC00E R/WCY7C67200 Breakpoint Register 0xC014 R/WForce Select USB Diagnostic Register 0xC03C R/WCY7C67200 Pull-downStrobe Watchdog Timer Register 0xC00C R/WCY7C67200 LockCY7C67200 Timer n Register R/WUSB n Control Register R/W Resistors Enable0xC094/0xC0B4 CY7C67200Pull up/Pull down on D+ and 0xC090/0xC0B0Sync Host n Control Register R/WCY7C67200 SequenceCY7C67200 Host n Address Register R/WHost n Count Register R/W Length Host n Endpoint Status Register RCY7C67200 CY7C67200 Host n PID Register WCY7C67200 Host n Count Result Register RHost n Device Address Register W Port A Connect Host n Interrupt Enable Register R/WCY7C67200 Port A Connect Host n Status Register R/WCY7C67200 CY7C67200 Host n SOF/EOP Count Register R/WHost n SOF/EOP Counter Register R CY7C67200 Host n Frame Register RDevice n Endpoint n Control Register R/W CY7C67200 CY7C67200 Device n Endpoint n Address Register R/WDevice n Endpoint n Count Register R/W CY7C67200 Device n Endpoint n Status Register R/WSetup Page 32 of CY7C67200CY7C67200 Device n Endpoint n Count Result Register R/WCY7C67200 Device n Interrupt Enable Register R/WInterrupt Enable Page 35 of CY7C67200CY7C67200 Device n Address Register WDevice n Status Register R/W Page 37 of CY7C67200CY7C67200 Device n Frame Number Register RDevice n SOF/EOP Count Register W C098H OTG Control Register 0xC098 R/WCY7C67200 CY7C67200 GPIO Control Register 0xC006 R/WCY7C67200 GPIO 0 Output Data Register 0xC01E R/WGPIO 1 Output Data Register 0xC024 R/W CY7C67200 GPIO 0 Input Data Register 0xC020 RGPIO 1 Input Data Register 0xC026 R GPIO 0 Direction Register 0xC022 R/WCY7C67200 GPIO 1 Direction Register 0xC028 R/WCY7C67200 HSS Control Register 0xC070 R/WCY7C67200 HSS Baud Rate Register 0xC072 R/WCY7C67200 HSS Transmit Gap Register 0xC074 R/WHSS Data Register 0xC076 R/W CY7C67200 HSS Receive Address Register 0xC078 R/WHSS Receive Counter Register 0xC07A R/W CY7C67200 HSS Transmit Address Register 0xC07C R/WHSS Transmit Counter Register 0xC07E R/W CY7C67200 HPI Breakpoint Register 0x0140 RInterrupt Routing Register 0x0142 R CY7C67200 SOF/EOP2 to CPU Enable BitCY7C67200 SIEXmsg Register WHPI Mailbox Register 0xC0C6 R/W CY7C67200 HPI Status Port HPI RCY7C67200 SPI Configuration Register 0xC0C8 R/WCY7C67200 3Wire Enable BitReceive Bit Length SPI Control Register 0xC0CA R/WCY7C67200 StrobeCY7C67200 SPI Interrupt Enable Register 0xC0CC R/WSPI Status Register 0xC0CE R CY7C67200 SPI Interrupt Clear Register 0xC0D0 WSPI CRC Control Register 0xC0D2 R/W CY7C67200 SPI CRC Value Register 0xC0D4 R/WSPI Data Register 0xC0D6 R/W CY7C67200 SPI Transmit Address Register 0xC0D8 R/WSPI Transmit Count Register 0xC0DA R/W CY7C67200 SPI Receive Address Register 0xC0DC R/WSPI Receive Count Register 0xC0DE R/W CY7C67200 UART Control Register 0xC0E0 R/WUART Status Register 0xC0E2 R CY7C67200 UART Data Register 0xC0E4 R/WCY7C67200 Pin DiagramPin Descriptions Type CY7C67200Table 38.Pin Descriptions continued NameCY7C67200 Absolute Maximum RatingsOperating Conditions Crystal Requirements XTALIN, XTALOUTCY7C67200 DC CharacteristicsCY7C67200 AC Timing CharacteristicsReset Timing nRESET nRD or nWRL or nWRHCY7C67200 Clock Timing1. I2C EEPROM Bus Timing - Serial I/O XTALINtCYC ADDR nCS nWR nRD DoutCY7C67200 tASU tCSSUCY7C67200 ADDRHSS BYTE and BLOCK Mode Receive CY7C67200HSS BYTE Mode Transmit HSS Block Mode TransmitPage 72 of CY7C67200Hardware CTS/RTS Handshake CY7C67200 Register SummaryDefault High Default Low+ Feedback Default HighDefault Low CY7C67200+ Feedback Default HighDefault Low CY7C67200+ Feedback Default HighDefault Low CY7C67200Table 43.Ordering Information Package DiagramOrdering Information CY7C67200Mode” Document History Page“Interrupt Enable Register 0xC00E R/W” CY7C67200