Manuals / Cypress / Computer Equipment / Computer Drive

Cypress CY7C67200 manual Introduction, Processor Core Functional Overview, Interface Descriptions

Models: CY7C67200

1 78

Download 78 pages 5 Kb

Page 2

Introduction

CY7C67200

Introduction

EZ-OTG™ (CY7C67200) is Cypress Semiconductor’s first USB On-The-Go (OTG) host/peripheral controller. EZ-OTG is designed to easily interface to most high-performance CPUs to add USB host functionality. EZ-OTG has its own 16-bit RISC processor to act as a coprocessor or operate in standalone mode. EZ-OTG also has a programmable IO interface block allowing a wide range of interface options.

Processor Core Functional Overview

An overview of the processor core components are presented in this section.

Processor

EZ-OTG has a general purpose 16-bit embedded RISC processor that runs at 48 MHz.

Clocking

EZ-OTG requires a 12 MHz source for clocking. Either an external crystal or TTL-level oscillator may be used. EZ-OTG has an internal PLL that produces a 48 MHz internal clock from the 12 MHz source.

Memory

EZ-OTG has a built-in 4K × 16 masked ROM and an 8K × 16 internal RAM. The masked ROM contains the EZ-OTG BIOS. The internal RAM can be used for program code or data.

Table 1. Interface Options for GPIO Pins

Interrupts

EZ-OTG provides 128 interrupt vectors. The first 48 vectors are hardware interrupts and the following 80 vectors are software interrupts.

General Timers and Watchdog Timer

EZ-OTG has two built-in programmable timers and a watchdog timer. All three timers can generate an interrupt to the EZ-OTG.

Power Management

EZ-OTG has one main power-saving mode, Sleep. Sleep mode pauses all operations and provides the lowest power state.

Interface Descriptions

EZ-OTG has a variety of interface options for connectivity, with several interface options available. See Table 1 to understand how the interfaces share pins and can coexist. Below are some general guidelines:

•I2C EEPROM and OTG do not conflict with any interfaces

•HPI is mutually exclusive to HSS, SPI, and UART

	GPIO Pins	HPI	HSS	SPI	UART	I2C	OTG
	GPIO31					SCL/SDA
	GPIO30					SCL/SDA
	GPIO29						OTGID
	GPIO24	INT
	GPIO23	nRD
	GPIO22	nWR
	GPIO21	nCS
	GPIO20	A1
	GPIO19	A0
	GPIO15	D15	CTS
	GPIO14	D14	RTS
	GPIO13	D13	RXD
	GPIO12	D12	TXD
	GPIO11	D11		MOSI
	GPIO10	D10		SCK
	GPIO9	D9		nSSI
	GPIO8	D8		MISO
	GPIO7	D7			TX
	GPIO6	D6			RX
	GPIO5	D5
	GPIO4	D4
	GPIO3	D3
	GPIO2	D2
	GPIO1	D1
	GPIO0	D0
Document #: 38-08014 Rev. *G							Page 2 of 78

[+] Feedback

Image 2

Cypress CY7C67200 manual Introduction, Processor Core Functional Overview, Interface Descriptions

Contents

Typical Applications EZ-OTG FeaturesCY7C67200 CY7C67200Interface Descriptions IntroductionProcessor Core Functional Overview CY7C67200OTG Features USB FeaturesUSB Pins OTG PinsI2C EEPROM Features UART FeaturesUART Pins I2C EEPROM PinsCY7C67200 HPI FeaturesHPI Pins CY7C67200Booster Pins Charge Pump FeaturesCharge Pump Pins CY7C67200Standalone Mode Crystal PinsCoprocessor Mode CY7C67200Figure 5. Minimum Standalone Hardware Configuration - Peripheral Only Power Savings and Reset DescriptionMinimum Hardware Requirements for Standalone Mode - Peripheral Only Power Savings Mode DescriptionInternal Memory LCP Variables USB Registers Slave Setup Packet BIOS StackMemory Map 0x0000 - 0x00FF 0x0100 - 0x011F 0x0120 - 0x013FCY7C67200 RegistersCPU Flags Register 0xC000 R CY7C67200 Bank Register 0xC002 R/WHardware Revision Register 0xC004 R CPU Speed Register 0xC008 R/W CY7C67200Power Control Register 0xC00A R/W CY7C67200Interrupt Enable Register 0xC00E R/W CY7C67200Breakpoint Register 0xC014 R/W CY7C67200Pull-down USB Diagnostic Register 0xC03C R/WCY7C67200 Force SelectLock Watchdog Timer Register 0xC00C R/WCY7C67200 StrobeResistors Enable Timer n Register R/WUSB n Control Register R/W CY7C672000xC090/0xC0B0 CY7C67200Pull up/Pull down on D+ and 0xC094/0xC0B4Sequence Host n Control Register R/WCY7C67200 SyncCY7C67200 Host n Address Register R/WHost n Count Register R/W Length Host n Endpoint Status Register RCY7C67200 Host n PID Register W CY7C67200CY7C67200 Host n Count Result Register RHost n Device Address Register W Port A Connect Host n Interrupt Enable Register R/WCY7C67200 Port A Connect Host n Status Register R/WCY7C67200 CY7C67200 Host n SOF/EOP Count Register R/WHost n SOF/EOP Counter Register R CY7C67200 Host n Frame Register RDevice n Endpoint n Control Register R/W CY7C67200 CY7C67200 Device n Endpoint n Address Register R/WDevice n Endpoint n Count Register R/W CY7C67200 Device n Endpoint n Status Register R/WSetup CY7C67200 Page 32 ofDevice n Endpoint n Count Result Register R/W CY7C67200CY7C67200 Device n Interrupt Enable Register R/WInterrupt Enable CY7C67200 Page 35 ofCY7C67200 Device n Address Register WDevice n Status Register R/W CY7C67200 Page 37 ofCY7C67200 Device n Frame Number Register RDevice n SOF/EOP Count Register W C098H OTG Control Register 0xC098 R/WCY7C67200 GPIO Control Register 0xC006 R/W CY7C67200CY7C67200 GPIO 0 Output Data Register 0xC01E R/WGPIO 1 Output Data Register 0xC024 R/W GPIO 0 Direction Register 0xC022 R/W GPIO 0 Input Data Register 0xC020 RGPIO 1 Input Data Register 0xC026 R CY7C67200GPIO 1 Direction Register 0xC028 R/W CY7C67200HSS Control Register 0xC070 R/W CY7C67200HSS Baud Rate Register 0xC072 R/W CY7C67200CY7C67200 HSS Transmit Gap Register 0xC074 R/WHSS Data Register 0xC076 R/W CY7C67200 HSS Receive Address Register 0xC078 R/WHSS Receive Counter Register 0xC07A R/W CY7C67200 HSS Transmit Address Register 0xC07C R/WHSS Transmit Counter Register 0xC07E R/W CY7C67200 HPI Breakpoint Register 0x0140 RInterrupt Routing Register 0x0142 R SOF/EOP2 to CPU Enable Bit CY7C67200CY7C67200 SIEXmsg Register WHPI Mailbox Register 0xC0C6 R/W HPI Status Port HPI R CY7C67200SPI Configuration Register 0xC0C8 R/W CY7C672003Wire Enable Bit CY7C67200Strobe SPI Control Register 0xC0CA R/WCY7C67200 Receive Bit LengthCY7C67200 SPI Interrupt Enable Register 0xC0CC R/WSPI Status Register 0xC0CE R CY7C67200 SPI Interrupt Clear Register 0xC0D0 WSPI CRC Control Register 0xC0D2 R/W CY7C67200 SPI CRC Value Register 0xC0D4 R/WSPI Data Register 0xC0D6 R/W CY7C67200 SPI Transmit Address Register 0xC0D8 R/WSPI Transmit Count Register 0xC0DA R/W CY7C67200 SPI Receive Address Register 0xC0DC R/WSPI Receive Count Register 0xC0DE R/W CY7C67200 UART Control Register 0xC0E0 R/WUART Status Register 0xC0E2 R UART Data Register 0xC0E4 R/W CY7C67200CY7C67200 Pin DiagramPin Descriptions Name CY7C67200Table 38.Pin Descriptions continued TypeCrystal Requirements XTALIN, XTALOUT Absolute Maximum RatingsOperating Conditions CY7C67200DC Characteristics CY7C67200nRESET nRD or nWRL or nWRH AC Timing CharacteristicsReset Timing CY7C67200XTALIN Clock Timing1. I2C EEPROM Bus Timing - Serial I/O CY7C67200tASU tCSSU ADDR nCS nWR nRD DoutCY7C67200 tCYCADDR CY7C67200HSS Block Mode Transmit CY7C67200HSS BYTE Mode Transmit HSS BYTE and BLOCK Mode ReceivePage 72 of CY7C67200Hardware CTS/RTS Handshake Default Low Register SummaryDefault High CY7C67200CY7C67200 Default HighDefault Low + FeedbackCY7C67200 Default HighDefault Low + FeedbackCY7C67200 Default HighDefault Low + FeedbackCY7C67200 Package DiagramOrdering Information Table 43.Ordering InformationCY7C67200 Document History Page“Interrupt Enable Register 0xC00E R/W” Mode”