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Cypress CY7C67200 manual Host n SOF/EOP Count Register R/W, Host n SOF/EOP Counter Register R

Models: CY7C67200

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Host n SOF/EOP Count Register [R/W]

CY7C67200

Host n SOF/EOP Count Register [R/W]

•Host 1 SOF/EOP Count Register 0xC092

•Host 2 SOF/EOP Count Register 0xC0B2

Figure 27. Host n SOF/EOP Count Register

Bit #	15		14	13	12	11		10	9	8
Field	Reserved						Count...
Read/Write	-		-	R/W	R/W	R/W		R/W	R/W	R/W
Default	0		0	1	0	1		1	1	0

Bit #	7	6	5	4		3	2	1	0
Field					...Count
Read/Write	R/W	R/W	R/W	R/W		R/W	R/W	R/W	R/W
Default	1	1	1	0		0	0	0	0

Register Description

The Host n SOF/EOP Count register contains the SOF/EOP Count Value that is loaded into the SOF/EOP counter. This value is loaded each time the SOF/EOP counter counts down to zero. The default value set in this register at power-up is 0x2EE0, which will generate a 1-ms time frame. The SOF/EOP counter is a down counter decremented at a 12-MHz rate. When this register is read, the value returned is the programmed SOF/EOP count value.

Count (Bits [13:0])

The Count field sets the SOF/EOP counter duration.

Reserved

All reserved bits must be written as ‘0’.

Host n SOF/EOP Counter Register [R]

•Host 1 SOF/EOP Counter Register 0xC094

•Host 2 SOF/EOP Counter Register 0xC0B4

Figure 28. Host n SOF/EOP Counter Register

Bit #	15		14	13	12	11		10	9	8
Field	Reserved						Counter...
Read/Write	-		-	R	R	R		R	R	R
Default	X		X	X	X	X		X	X	X

Bit #	7	6	5	4		3	2	1	0
Field					...Counter
Read/Write	R	R	R	R		R	R	R	R
Default	X	X	X	X		X	X	X	X

Register Description

The Host n SOF/EOP Counter register contains the current value of the SOF/EOP down counter. This value can be used to determine the time remaining in the current frame.

Counter (Bits [13:0])

The Counter field contains the current value of the SOF/EOP down counter.

Document #: 38-08014 Rev. *G

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Cypress CY7C67200 manual Host n SOF/EOP Count Register R/W, Host n SOF/EOP Counter Register R

Contents

CY7C67200 EZ-OTG FeaturesCY7C67200 Typical ApplicationsCY7C67200 IntroductionProcessor Core Functional Overview Interface DescriptionsOTG Pins USB FeaturesUSB Pins OTG FeaturesI2C EEPROM Pins UART FeaturesUART Pins I2C EEPROM FeaturesCY7C67200 HPI FeaturesHPI Pins CY7C67200CY7C67200 Charge Pump FeaturesCharge Pump Pins Booster PinsCY7C67200 Crystal PinsCoprocessor Mode Standalone ModePower Savings Mode Description Power Savings and Reset DescriptionMinimum Hardware Requirements for Standalone Mode - Peripheral Only Figure 5. Minimum Standalone Hardware Configuration - Peripheral Only0x0000 - 0x00FF 0x0100 - 0x011F 0x0120 - 0x013F LCP Variables USB Registers Slave Setup Packet BIOS StackMemory Map Internal MemoryRegisters CPU Flags Register 0xC000 RCY7C67200 Bank Register 0xC002 R/W Hardware Revision Register 0xC004 RCY7C67200 CY7C67200 CPU Speed Register 0xC008 R/WCY7C67200 Power Control Register 0xC00A R/WCY7C67200 Interrupt Enable Register 0xC00E R/WCY7C67200 Breakpoint Register 0xC014 R/WForce Select USB Diagnostic Register 0xC03C R/WCY7C67200 Pull-downStrobe Watchdog Timer Register 0xC00C R/WCY7C67200 LockCY7C67200 Timer n Register R/WUSB n Control Register R/W Resistors Enable0xC094/0xC0B4 CY7C67200Pull up/Pull down on D+ and 0xC090/0xC0B0Sync Host n Control Register R/WCY7C67200 SequenceHost n Address Register R/W Host n Count Register R/WCY7C67200 Host n Endpoint Status Register R CY7C67200Length CY7C67200 Host n PID Register WHost n Count Result Register R Host n Device Address Register WCY7C67200 Host n Interrupt Enable Register R/W CY7C67200Port A Connect Host n Status Register R/W CY7C67200Port A Connect Host n SOF/EOP Count Register R/W Host n SOF/EOP Counter Register RCY7C67200 Host n Frame Register R Device n Endpoint n Control Register R/WCY7C67200 CY7C67200 Device n Endpoint n Address Register R/W Device n Endpoint n Count Register R/WCY7C67200 Device n Endpoint n Status Register R/W SetupCY7C67200 Page 32 of CY7C67200CY7C67200 Device n Endpoint n Count Result Register R/WDevice n Interrupt Enable Register R/W Interrupt EnableCY7C67200 Page 35 of CY7C67200Device n Address Register W Device n Status Register R/WCY7C67200 Page 37 of CY7C67200Device n Frame Number Register R Device n SOF/EOP Count Register WCY7C67200 OTG Control Register 0xC098 R/W CY7C67200C098H CY7C67200 GPIO Control Register 0xC006 R/WGPIO 0 Output Data Register 0xC01E R/W GPIO 1 Output Data Register 0xC024 R/WCY7C67200 CY7C67200 GPIO 0 Input Data Register 0xC020 RGPIO 1 Input Data Register 0xC026 R GPIO 0 Direction Register 0xC022 R/WCY7C67200 GPIO 1 Direction Register 0xC028 R/WCY7C67200 HSS Control Register 0xC070 R/WCY7C67200 HSS Baud Rate Register 0xC072 R/WHSS Transmit Gap Register 0xC074 R/W HSS Data Register 0xC076 R/WCY7C67200 HSS Receive Address Register 0xC078 R/W HSS Receive Counter Register 0xC07A R/WCY7C67200 HSS Transmit Address Register 0xC07C R/W HSS Transmit Counter Register 0xC07E R/WCY7C67200 HPI Breakpoint Register 0x0140 R Interrupt Routing Register 0x0142 RCY7C67200 CY7C67200 SOF/EOP2 to CPU Enable BitSIEXmsg Register W HPI Mailbox Register 0xC0C6 R/WCY7C67200 CY7C67200 HPI Status Port HPI RCY7C67200 SPI Configuration Register 0xC0C8 R/WCY7C67200 3Wire Enable BitReceive Bit Length SPI Control Register 0xC0CA R/WCY7C67200 StrobeSPI Interrupt Enable Register 0xC0CC R/W SPI Status Register 0xC0CE RCY7C67200 SPI Interrupt Clear Register 0xC0D0 W SPI CRC Control Register 0xC0D2 R/WCY7C67200 SPI CRC Value Register 0xC0D4 R/W SPI Data Register 0xC0D6 R/WCY7C67200 SPI Transmit Address Register 0xC0D8 R/W SPI Transmit Count Register 0xC0DA R/WCY7C67200 SPI Receive Address Register 0xC0DC R/W SPI Receive Count Register 0xC0DE R/WCY7C67200 UART Control Register 0xC0E0 R/W UART Status Register 0xC0E2 RCY7C67200 CY7C67200 UART Data Register 0xC0E4 R/WPin Diagram Pin DescriptionsCY7C67200 Type CY7C67200Table 38.Pin Descriptions continued NameCY7C67200 Absolute Maximum RatingsOperating Conditions Crystal Requirements XTALIN, XTALOUTCY7C67200 DC CharacteristicsCY7C67200 AC Timing CharacteristicsReset Timing nRESET nRD or nWRL or nWRHCY7C67200 Clock Timing1. I2C EEPROM Bus Timing - Serial I/O XTALINtCYC ADDR nCS nWR nRD DoutCY7C67200 tASU tCSSUCY7C67200 ADDRHSS BYTE and BLOCK Mode Receive CY7C67200HSS BYTE Mode Transmit HSS Block Mode TransmitCY7C67200 Hardware CTS/RTS HandshakePage 72 of CY7C67200 Register SummaryDefault High Default Low+ Feedback Default HighDefault Low CY7C67200+ Feedback Default HighDefault Low CY7C67200+ Feedback Default HighDefault Low CY7C67200Table 43.Ordering Information Package DiagramOrdering Information CY7C67200Mode” Document History Page“Interrupt Enable Register 0xC00E R/W” CY7C67200